Zynq Ultrascale+ Rfsoc Zu49Dr Features And Resources - Xilinx Zynq UltraScale+ ZCU216 User Manual

PL CPU reset pushbutton
○
PL User RGB LEDs (24 total, 8 each R, G, B)
○
PL PMOD0/1 (2 R.A. 2x6 Receptacles)
○
• Security—PSBATT button battery backup
• SYSMON Header
• Operational Switches (Power on/off, PS_PROG_B, Boot mode DIP switch)
• Operational Status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power Management
• System Controller (MSP430)
The ZCU216 provides designers a rapid prototyping platform that uses the
XCZU49DR-2FFVF1760 device. The ZU49DR contains many useful processor system (PS) hard
block peripherals exposed through the multi-use I/O (MIO) interface and a variety of FPGA
programmable logic. The following table lists a brief summary of the resources available within
the ZU49DR. A feature set overview, description, and ordering information is provided in the
Zynq UltraScale+ RFSoC Data Sheet: Overview (DS889).
Table 1: Zynq UltraScale+ RFSoC ZU49DR Features and Resources
14-bit 2.5 GSPS RF-DAC with DDC
14-bit 10 GSPS RF-DAC with DUC
APU: Quad-core Arm
RTPU: Dual-core Arm
HD I/O
HP I/O
MIO banks
PS GTR 6 Gb/s transceivers
PL GTY 28 Gb/s transceivers
System Logic Cells
CLB Flip-Flops
CLB LUTs
Max. Distributed RAM (Mb)
Block RAM Blocks
UltraRAM Blocks
DSP Slices
PCIe ® Gen3 x16 / Gen4 x8 / CCIX (3)
150G Interlaken
100G Ethernet w/ RS-FEC
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Feature
® Cortex™-A53 MPCore with CoreSight™
® Cortex™-R5F MPCore with CoreSight
Chapter 1: Introduction
Resource Count
16
16
1
1
96
312
3 banks, total of 78 pins
4 PS-GTRs
16 GTYs
930, 300
850, 560
425, 280
13.0
1080 (38 Mb)
80 (22.5 Mb)
4,272
2
1
2
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