Mitsubishi FX3U Series Programming Manual page 453

FX /FX Series Programmable Controllers
3U 3UC
Programming Manual - Basic & Applied Instruction Edition
Set item
Derivative time (TD)
S +6
3
+7
S
3
: These devices are occupied for internal processing in PID control loop. Do not change the data.
S +19
3
Input variation
*1
(incremental) alarm set
S +20
3
value
Input variation
*1
(decremental) alarm set
S +21
3
value
Output variation
(incremental) alarm set
value
*1
S +22
3
Output upper limit set value −32768 to 32767
Output variation
(decremental) alarm set
value
*1
S +23
3
Output lower limit set value −32768 to 32767
*1
Alarm output
S +24
3
The setting below is required when the limit cycle method is used (when bit 6 is set to "ON" in the operation setting (ACT)).
PV value threshold
S +25
3
(hysteresis) width (SHPV)
Output value upper limit
S +26
3
(ULV)
Output value lower limit
S +27
3
(LLV)
Wait setting from end of
tuning cycle to start of PID
S +28
3
control (Kw)
*1. +20 to
S
3
setting (ACT).
Contents of setting
0 to 32767 (× 10 ms)
0 to 32767
0 to 32767
0 to 32767
0 to 32767
0: Input variation (incremental) is
not exceeded.
bit0
1: Input variation (incremental) is
exceeded.
0: Input variation (decremental) is
not exceeded.
bit1
1: Input variation (decremental) is
exceeded.
0: Output variation (incremental) is
not exceeded.
bit2
1: Output variation (incremental) is
exceeded.
0: Output variation (decremental) is
not exceeded.
bit3
1: Output variation (decremental) is
exceeded.
Set it according to the fluctuation of
the measured value (MV).
Set the maximum value (ULV) of
the output value (MV).
Set the minimum value (LLV) of the
output value (MV).
−50 to 32717%
+24 are occupied when bit 1, bit 2 or bit 5 is set to "1" in
S
3
16 External FX Device – FNC 80 to FNC 89
16.7 FNC 88 – PID / PID Control Loop
Remarks
When "0" is set, the derivative operation is
not executed.
It is valid when bit 1 is set to "1" in
for the operation setting (ACT).
It is valid when bit 1 is set to "1" in
for the operation setting (ACT).
It is valid when bit 2 is set to "1" and bit 5 is
set to "0" in S +1 for the operation
3
setting (ACT).
It is valid when bit 2 is set to "0" and bit 5 is
set to "1" in S +1 for the operation
3
setting (ACT).
It is valid when bit 2 is set to "1" and bit 5 is
set to "0" in +1 for the operation
S
3
setting (ACT).
It is valid when bit 2 is set to "0" and bit 5 is
set to "1" in S +1 for the operation
3
setting (ACT).
It is valid when bit 1 is set to "1" or bit 2 is set
to "1" in S +1 for the operation setting
3
(ACT).
They are occupied when bit 6 is set to "ON
(limit cycle method)" in the operation setting
(ACT).
+1 for operation
S
3
11
12
S +1
3
S +1
3
13
14
15
16
17
18
19
20
451