Pci Express Gen2; Table 1-4 Pci Express Gen3 Interfaces To Pcie Connector; Table 1-5 Pci Express Gen3 Interfaces To M.2 Modules; Table 1-6 Pci Express Gen2 (Pch) Interfaces - SMART Embedded Computing MC1600 Installation And Use Manual

System Overview
Table 1-4
IIO
CPU
Port
CPU1 PE1
CPU2 PE1
On the Extreme Edge Server, the x8 port (PE2) of each CPU is bifurcated into two x4 ports.
These ports connect to the M.2 NVMe modules according to the following table.
Table 1-5
CPU
CPU1
CPU1
CPU2
1.7.1.2

PCI Express Gen2

The Integrated PCH Logic additionally implements eight lanes of PCIe Gen2 that can be
split into eight root ports. The ports support Gen1 (2.5Gb/s) and Gen2 (5Gb/s) speeds.
Lanes 1-4 and lanes 5-8 can independently be configured as four x1, two x2, one x2 and
two x1, or one x4 port(s).
On the Extreme Edge Server, lanes 1-4 of CPU1 and CPU2 are configured as four x1 ports.
These ports are connected according to the following table. Default routing of the second
MAC/PHY is to CPU2 on dual-CPU variants, and to CPU1 on single-CPU variants.
Table 1-6
CPU
CPU1
CPU1
CPU1
CPU2
CPU1
56
PCI Express Gen3 Interfaces to PCIe Connector
IIO Port Bifurcated
Lanes Port
<7:0> 1
<7:0> 1
PCI Express Gen3 Interfaces to M.2 Modules
IIO Port
IIO Port
Lanes
PE2 <3:0>
PE2 <7:4>
PE2 <3:0>
PCI Express Gen2 (PCH) Interfaces
PCH PCIe
Port (Lane) Destination
Port Group
Lanes 1-4 1
Lanes 1-4 2
Lanes 1-4 3
Lanes 1-4 3
Lanes 1-4 4
MC1600 Extreme Edge Server Installation and Use (6806870A02B)
Bifurcated Destination
Port Lanes (PCIe Connector Signals)
<7:0> PETp/PETn<7:0> and PERp/PERn <7:0>
PETp/PETn<15:8> and PERp/PERn
<7:0>
<15:8>
Bifurcated Bifurcated Port
Port Lanes
1 <3:0>
2 <3:0>
1 <3:0>
Ethernet Switch
Ethernet MAC/PHY A
Ethernet MAC/PHY B (option)
Ethernet MAC/PHY B (default)
BMC
System Overview
Destination
M.2 (Primary)
M.2 (Secondary)
M.2
Link Speed
5.0Gbps (Gen2)
2.5Gbps (Gen1)
2.5Gbps (Gen1)
2.5Gbps (Gen1)
2.5Gbps (Gen1)