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Kontron cPCI-DXS64 Technical Reference Manual

Kontron cPCI-DXS64 Technical Reference Manual

6u compactpci 64-bit system dual processor
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cPCI-DXS64
®
6U CompactPCI
64-bit System Dual Processor
Technical Reference Manual
Version 1.3, February 2003
Note: The latest releases of the Technical Reference Manuals are available at:
ftp://ftp.kontron.ca/Support/Product_Manuals/
www.kontron.com
Ref. : M6001_TECH (board revision 0)

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Summary of Contents for Kontron cPCI-DXS64

  • Page 1 ® 6U CompactPCI 64-bit System Dual Processor Technical Reference Manual Version 1.3, February 2003 Note: The latest releases of the Technical Reference Manuals are available at: ftp://ftp.kontron.ca/Support/Product_Manuals/ www.kontron.com Ref. : M6001_TECH (board revision 0)
  • Page 2 FCC COMPLIANCE STATEMENT Warning Changes or modifications to this unit not expressly approved by the party responsible for the compliance could void the user’s authority to operate this equipment. This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC rules.
  • Page 3 This document may contain information or refer to products protected by the copyrights or patents of others and does not convey any license under the patent rights of Kontron, nor the rights of others. Printed in Canada.
  • Page 4 READ ME FIRST Your computer board has a standard non-rechargeable lithium battery. To preserve the battery lifetime, the battery enable jumper is removed when you receive the board. If you do not have any jumper cap, we suggest you to use the Watchdog Timer jumper cap. EXERCISE CAUTION WHILE REPLACING LITHIUM BATTERY WARNING Danger of explosion if battery is incorrectly replaced.
  • Page 5 Support department for further assistance. ADAPTER CABLES While adapter cables are provided from various sources, the pinout is often different. The direct crimp design offered by Kontron allows the simplest cable assembly. All cables are available from Kontron Sales Department.
  • Page 6 After opening the box, save it and the packing material for possible future shipment. Remove the board from its antistatic wrapping and place it on a grounded surface. Inspect the board for damage. If there is any damage, or items are missing, inform immediately Kontron. When unpacking you will find: ®...
  • Page 7 1.4. Hot Swap capability................... 1-7 1.5. Interfacing with the Environment ............... 1-9 1.5.1. CPCI ........................1-9 1.5.2. Mezzanine ......................1-9 1.6. Compatibility with other KONTRON Products ..........1-10 1.7. Mezzanine Card Concept................1-11 1.7.1. Kontron’s Mezzanine Concept ................1-11 1.7.2. CompactFlash Feature ..................1-12 1.8.
  • Page 8 2.1.1. Setups........................2-1 2.2. Enhanced IDE Interfaces .................. 2-2 2.3. Ethernet Interfaces .................... 2-3 2.3.1. Front Plate Configuration..................2-3 2.3.2. CPCI I/O Configuration..................2-3 2.4. Floppy Disk Interface..................2-4 2.5. PS/2 Keyboard / PS/2 Mouse Interface............. 2-4 2.6. Parallel Port....................... 2-5 2.6.1. Standard Mode....................2-6 2.6.2.
  • Page 9 3.2.9.2. Dual-stage Watchdog ................3-7 3.2.9.3. Power Failure Detection ............... 3-9 3.2.10. Reset History....................3-10 3.2.11. Register BITs description (summary)..............3-11 3.3. Onboard Interconnectivity ................3-12 3.3.1. cPCI-DXS64 Block Diagram ................3-12 ® 3.3.2. Pentium III processor ..................3-13 3.3.3. Onboard Connectors and Headers ..............3-13 3.3.4.
  • Page 10 3.5.3. Storage Devices ....................3-24 3.5.4. Power Supply ....................3-24 3.5.5. Fan Tray......................3-24 3.5.6. Installing the Board into a Bay ................3-24 3.5.7. Connector Keying.....................3-25 3.5.8. Bus Mastering ....................3-25 3.5.9. Connection .......................3-25 3.6. CPCI I/O Signals ..................... 3-26 3.6.1. J3 Signal Specification ..................3-26 3.6.1.1.
  • Page 11 3.6.3.8. Keyboard Interface ................3-36 3.6.3.9. Mouse Interface...................3-36 SOFTWARE SETUP..................4-1 4.1. PHOENIX BIOS Setup Program................ 4-1 4.1.1. Accessing the BIOS setup program ..............4-1 4.1.2. The Menu Bar.....................4-3 4.1.2.1. The Legend Bar..................4-4 4.1.2.2. The Field Help Window................. 4-4 4.1.2.3. The General Help Windows..............4-5 4.1.2.4.
  • Page 12 PART FIVE – Installation and Settings MEMORY & I/O MAPS Memory Mapping ........................A-1 I/O Mapping ........................A-2 INTERRUPT LINES IRQ Lines........................B-1 DMA Channels......................B-1 BOARD DIAGRAMS Top Devices Surface Mount ....................C-1 BOTTOM DEVICE SURFACE MOUNT.................. C-2 C.3 Mounting Holes ......................C-3 C.4 Connector Holes ......................
  • Page 13 D.14 J23, Mezzanine (64-BIT/66MHZ) ................D-11 D.15 J21, PS/2 Mouse & Keyboard ..................D-11 D.16 J22, mezzanine HA connector ..................D-12 D.17 J24, Ethernet 1 and 2....................D-12 D.18 J25, Hot Swap Switch ....................D-13 D.19 SW1 – Reset Switch ....................D-13 D.20 SW2 –...
  • Page 14 1. PRODUCT DESCRIPTION PRODUCT OVERVIEW BOARD SPECIFICATIONS PRODUCT OPTIONS HOT SWAP CAPABILITY INTERFACING WITH THE ENVIRONMENT COMPATIBILITY WITH KONTRON PRODUCTS MEZZANINE CONCEPTS OVERVIEW OF THE INTEL’S 840 CHIPSET...
  • Page 15 Rear I/O CPCI connectors are PICMG 2.0 Rev 3.0 compliant. CompactPCI connectors are located at the rear edge of the processor board. The complete CPCI connector configuration of the cPCI-DXS64 is composed of four connectors referred to as J1, J2, J3, J4, and J5. Their function is described below:...
  • Page 16 Video AGP 2X • SMBus (for system management of CPU temperature monitoring, DRAM control, and power monitoring) • Kontron embedded mezzanine for second PCI bus, SCSI, and EIDE • Cache Memory 16K/16K Instruction / Data CPU-internal Level 1 • 256KB 64-bit wide on-die Level 2 Advanced Transfer Cache •...
  • Page 17 Ethernet Two 10/100Mb/s Ethernet, PCI 10/100Base-TX ports (Intel 82559 controller) HD Mezzanine Card: Optionally onboard using Kontron’s cMC series mezzanine cards. HD Mezzanine Card Always Onboard SCSI PCI-ULTRA160 (Ultra3) LVDS SCSI supports up to 320 MB/s dual channel or 160 MB/s single channel...
  • Page 18 Technical Reference manual Board Specifications (continued) Two-stage software programmable Watchdog timer drives NMI on Supervisory first stage and system reset on second stage. Time out from 16msec to 4.5min Hardware system monitor • Power failure detector • Low battery voltage detector •...
  • Page 19 Supply Current:* +3.3V, 4.5 Amps maximum +5V, 9 Amps maximum +12V, 0.1 Amps maximum Power Dissipation cPCI-DXS64 : 60W maximum *Tested with Pentium III processor 600Mhz and 1GB RAMBUS Operating Storage and Transit Environmental Temperature 0-50°C / 32-122°F -40 to +70°C / -40 to 158°F Humidity 5% to 95% @ 40°C/104°F...
  • Page 20 Technical Reference manual 1.3. PRODUCT OPTIONS The cPCI-DXS64 can be purchased either for front plate I/O interfacing (video serial port, Ethernet) or RTM (Rear Transition Module) I/O interfacing (no interconnection capability available on the front plate) through CPCI I/O connectors and backplane.
  • Page 21 Product Description 1.4. HOT SWAP CAPABILITY The cPCI-DXS64 supports Hot Swap capability which means that hot swappable boards can be removed from or installed in the system while online (without powering-down the system). Hot Swap consists of board hardware with the Hot Swap additions to the Hardware Connection Layer, and the Hot-Plug Service.
  • Page 22 Technical Reference manual The Software Connection Control resources on the board provide a signal (ENUM#) for system host notification and a switch and LED to interface with the operator. Full Hot Swap boards drive the ENUM# signal to the system host to indicate a service request.
  • Page 23 CPCI Passive Backplane. 1.5.2. Mezzanine The mezzanine is a hardware interface concept introduced by Kontron to increase the I/O connectivity of the cPCI-DXS64, but respecting the dual slot 6U form factor restrictions. The onboard mezzanine connector features PCI bus, and IDE signals, for mezzanine applications: Kontron provides a storage/bridging mezzanine with an optional hard drive.
  • Page 24 Technical Reference manual 1.6. COMPATIBILITY WITH OTHER KONTRON PRODUCTS The cPCI-DXS64 System Processor is a member of the Kontron’s CompactPCI product family. The boards are fully compliant with the PICMG 2.0 Rev.2.1 and PICMG 2.1 CompactPCI specifications. When building a basic environment around the cPCI-DXS64, the platform may be composed of any of the following devices: •...
  • Page 25 The capability of the cPCI-DXS64 to connect with other devices is enforced by PCI Mezzanine Cards (PMC). A fully equipped cPCI-DXS64 board may appear as follows: 1.7.1. Kontron’s Mezzanine Concept This is Kontron’s concept to expand the I/O capability of the board. It is built around two connectors: •...
  • Page 26 Technical Reference manual 1.7.2. CompactFlash Feature The cPCI-DXS64 board also supports standard CompactFlash disk through a CompactFlash module. CompactFlash disk is a method of storing and transferring data. It is supported on the board as a standard IDE drive and connects to the primary EIDE interface.
  • Page 27 Product Description 1.8. OVERVIEW OF THE INTEL’S 840 CHIPSET SYSTEM ARCHITECTURE The chipset contains three main components: • The 82840 Main Controller Hub (MCH) • The 82801 I/O Controller (ICH) • The 82802 Firmware Hub (FWH) 1.8.1. The 82840 Memory Controller Hub (MCH) 1-13...
  • Page 28 Technical Reference manual 1.8.1.1. The 82840 Memory Controller Hub provides: • The processor interface • The system bus interface • The memory controller (DRAM interface) • An AGP interface • A hub interface for I/O • A hub interface for PCI expansion.
  • Page 29 Product Description 1.8.2. The 82801 I/O Controller Hub (ICH) The ICH is a highly integrated multifunctional I/O Controller Hub that provides the interface to the PCI Bus and integrates many of the functions needed in today’s PC platforms. The MCH and ICH communicate over a dedicated hub interface. Functions and capabilities include: •...
  • Page 30 Technical Reference manual 1.8.4. The 82806 PCI 64 Hub (P64H) The PCI-64 Hub (P64H) is a peripheral chip that performs PCI bridging functions between the hub interface and the PCI Bus and is used as an integral part of the Intel® 840 chipset.
  • Page 31 Product Description 1.8.5.1. RDRAM Functional Description DRCG 1.8V Ω RSL Termination Resistor 82840 Rambus Clock 400MHz 4 RIMM sockets (Rambus In-line Memory Up to 2GB of RIMM sockets must be populated as J8-J9 : Same RIMM capacity. Must be first when using only 2 J11-J12: Same RIMM capacity.
  • Page 32 2. ONBOARD FEATURES COMPACTFLASH INTERFACE ENHANCED IDE INTERFACES ETHERNET INTERFACES FLOPPY DISK INTERFACE PS/2 KEYBOARD AND MOUSE INTERFACE PARALLEL PORT SERIAL PORTS THERMAL MANAGEMENT USB INTERFACES VIDEO INTERFACES...
  • Page 33 (typical M.T.B.F. is 1,000,000 hours) and low power. The cPCI-DXS64 supports all CompactFlash sizes presently available and future sizes when available. The C-Flash disk connects on the cPCI-DXS64 via the onboard Flash Disk connector. Related Jumpers cPCI-DXS64: W6 (5-6) to set the CompactFlash disk as master or slave.
  • Page 34 Technical Reference Manual 2.2. ENHANCED IDE INTERFACES The board features two channel Bus Master PCI EIDE dedicated to Primary and Secondary IDE logical interfaces. Each channel supports up to two IDE devices (including CD-ROMs, hard disks, plus CompactFlash on the secondary IDE interface) with independent timings, in Master/Slave combination.
  • Page 35 The Boot from LAN capability is supported. To enable the option, use the BIOS Setup program. Please refer to Section 4.1 PHOENIX BIOS Setup Program. A diskette entitled “Network Drivers for Intel 82559 is included with the cPCI-DXS64. It contains network drivers for most common operating systems.
  • Page 36 Technical Reference Manual 2.4. FLOPPY DISK INTERFACE The onboard floppy disk controller is IBM PC XT/AT compatible. It handles 3.5” and 5.25”, low and high density disks. Up to two drives can be supported in any combination. Signal Paths The Floppy Disk Controller interface is available through the CPCI I/O connector.
  • Page 37 Feature Description 2.6. PARALLEL PORT The cPCI-DXS64 features one multi-mode parallel port. It is compatible with Standard Mode IBM PC/XT, PC/AT, and PS/2 compatible bi-directional parallel port, Enhanced Parallel Port (EPP), and Enhanced Capabilities Port (ECP). Signal Path The Parallel Port interface is only available through J5 CPCI I/O connector.
  • Page 38 Technical Reference Manual 2.6.1. Standard Mode The Standard mode is unidirectional. It is supported to maintain the compatibility with the IBM PC standard. 2.6.2. EPP Mode The EPP (Enhanced Parallel Port) mode consists of a hardware independent method of accessing a parallel port configured as EPP.
  • Page 39 Feature Description 2.7. SERIAL PORTS Two full function serial ports are provided on the board for asynchronous serial communications. They are 16C550 high-speed UART compatible and support 16-byte FIFO buffers for transfer rates from 50bps to 115Kbps. Each serial port is specified as follows: Designation Communication Mode Output Path...
  • Page 40 Technical Reference Manual 2.7.2. Serial Port B Serial Port B is buffered directly for RS-232 operations and is 16C550 PC-Compatible. The interface includes the complete signal set for handshaking, modem control, interrupt generation, and data transfer. The Serial Port B port is 100% compatible with the IBM-AT serial port.
  • Page 41 CAUTION When installing the cPCI-DXS64 at one end of the network, W6 (1-2 and 3-4) jumper caps must be installed to connect the 120 ohms termination resistors...
  • Page 42 Technical Reference Manual 2.8. THERMAL MANAGEMENT The processor module includes a user-defined temperature sensor / alarm function, which provides thermal monitoring of the processor. Two temperature sensors are provided to supervise the thermal environment. One is used to monitor the CPU die temperature, while the second one, located on the CPU casing, allows the monitoring of the ambient temperature around the CPU.
  • Page 43 USB supports Plug and Play and hot swapping operations (OS level). These user-friendly features allow USB devices to be automatically attached, configured and detached, without reboot or running setup. The cPCI-DXS64 board fully supports the standard universal host controller interface (UHCI) and uses standard software drivers that are UHCI-compatible. 2.10. VIDEO INTERFACE The high-performance video capability of the board is based on Accelerated Graphics Port (AGP) technology.
  • Page 44 Technical Reference Manual Front Plate Configuration VGA interface signals are available on J4, standard VGA connector, located on the front plate of the board, only when the board is ordered for front access operations. This configuration allows direct connection of CRT display onto the board.
  • Page 45 3. INSTALLING THE BOARD SETTING JUMPERS REGISTER’S DESCRIPTION ONBOARD INTERCONNECTIVITY CUSTOMIZING THE BOARD BUILDING A CPCI SYSTEM CPCI I/O SIGNALS...
  • Page 46 3.1. SETTING JUMPERS 3.1.1. Jumper Description for the PCI-DXS64 Description Clear CMOS On position 1-2, all CMOS information is cleared. This jumper is set by default at position 2-3. Onboard Battery Connects or Disconnects the battery to/from the board circuitry. Onboard Video Use this jumper to disable the onboard video feature.
  • Page 47 Technical Reference Manual 3.1.2. PCI-DXS64 – Jumper Settings W1 Clear CMOS PCI AGP PCI AGP Controller Controller (440BX Chipset) 840 Chipset Vidéo sm s c Super I/O Controller Note 1 Defines Front or Rear access P64H for Ethernet 1 & 2 and Video...
  • Page 48 These registers are 8-bit wide and can be located at three different I/O base addresses: 190h. This section includes a description of each I/O register and bit available for programming and configuring the CPCI-DXS64. 3.2.2. Register 190h: Serial port B configuration. Reset...
  • Page 49 Technical Reference Manual 3.2.3. Register 191h: Reset History & CPU Fault Reset Read PBRES Write Used by the BIOS at runtime; do not write to this register. Reset history PBRES This bit is set when the reset button is pressed. It is cleared at power- up and when the bit CLRHIS* is "0"...
  • Page 50 Installing the Board 3.2.5. Register 193h: Silicon ID Chip Interface, Local I C, System Monitor Connector Interface Reset Read APPFLT* GPIO2 GPIO1 IDCHIP (pin) SCL (pin) SDA (pin) (pin) (pin) (pin) Write APPFLT* GPIO2 GPIO2 IDCHIP (reg.) SCL (reg.) SDA (reg.) (reg) (reg) (reg)
  • Page 51 Technical Reference Manual 3.2.8. Register 197h: NMI sources & mask Reset Read BatFltEn BatFlt FanFltEn FanFlt ExtFltEn ExtFlt WdNmiEn WdNmi Write BatFltEn FanFltEn ExtFltEn WdNmiEn Not used by the BIOS. WdNmi Watchdog NMI: NMI from the Watchdog timeout. WdNmiEn Enable NMI from the Watchdog.
  • Page 52 This feature is useful in embedded systems where human supervision is not required or impossible. The CPCI-DXS64 provides a two-stage digital watchdog with a software programmable timeout period. The watchdog can be enabled by software.
  • Page 53 Technical Reference Manual A variable refresh is possible as shown below: The programmable watchdog can be viewed as a decrementing counter that is initialized by a write to register 196h. The processor must initialize the counter to prevent it from reaching count 0 (timeout).
  • Page 54 Installing the Board The second stage times-out 1ms after the first one and generates a master reset. WDS[2,0] NMI Timeout RESET Timeout 15ms 0.015s + 8.06ms 62.5ms 0.0625s + 8.06ms 250ms 0.250s + 8.06ms 1s+ 8.06ms 4s + 8.06ms 16s + 8.06ms 64s + 8.06ms 256s 256 + 8.06ms...
  • Page 55 Technical Reference Manual 3.2.10. Reset History Following a reset, the application software can read the register 191h and examine the bits PBRES and WDO. Based on the values of those bits, the following conclusions can be drawn about the reset source.
  • Page 56 Installing the Board 3.2.11. Register BITs description (summary) Address CPLD READ 190* RS485 RS232 WRITE READ PBRST 191* WRITE READ WD_LO 192* _CLRHIS WRITE READ I2C_CL 193* IDCHIP I2C_DATA WRITE READ 194* _CND3 CIS3_1 CIS3_0 CBAS3_1 CBAS3_0 RESERVED WRITE READ RESERV.
  • Page 57 Technical Reference Manual 3.3. ONBOARD INTERCONNECTIVITY 3.3.1. cPCI-DXS64 Block Diagram INTEL PENTIUM III INTEL PENTIUM III (FC-PGA SOCKETABLE) (FC-PGA SOCKETABLE) +12 V +5 V +5 V +12 V 256KB 256KB CuMINE CPU CORE L2 CACHE CuMINE CPU CORE L2 CACHE VRM 8.4...
  • Page 58 Installing the Board ® 3.3.2. Pentium III processor The cPCI-DXS64 system board supports the Intel’s 600, 700 and 850MHz Pentium III processor (Higher clock speeds will be available when Intel will release the corresponding parts). ® It consists of a Pentium...
  • Page 59 Technical Reference Manual 3.3.4. Front Plate Connectors and Indicators Name Description Comments Standard 15-pin DSUB female Video Connector connector Use a small tool to press the Reset Button button and proceed to a hardware reset of the board Standard 9-pin DSUB male...
  • Page 60 Installing the Board 3.3.5. CompactPCI Connectors CPCI J5 Connector Supports PS/2 mouse, serial ports A and C, primary IDE channel, parallel port, keyboard, speaker, floppy disk, reset, USB, SMBus and power signals. CPCI J4 Connector Supports Ethernet1, secondary IDE channel, SCSI, VGA, and power signals.
  • Page 61 Technical Reference Manual 3.4. CUSTOMIZING THE BOARD 3.4.1. Processor and Fan Your board will be installed with Pentium III processors and their adequate cooling system. CAUTION Since CPUs are very sensitive components, particular attention should be given while installing a processor on the board. Improper installation may...
  • Page 62 Installing the Board 3.4.2. Backup Battery An onboard 3.6V lithium battery is provided to backup BIOS setup values and the real time lock (RTC). When replacing, the battery must be connected as follows: Lithium Battery 3.6V Negative Pin (outer) Positive Pin Onboard (inner) Battery...
  • Page 63 Technical Reference Manual 3.4.3. Memory The board supports 256MB or 1GB of 64/72-bit Rambus DRAM (RDRAM) divided into four RIMM sockets (J8, J9, J11 and J12). The minimum configuration is 128MB (2 X 64MB) NOTE All memory sockets must be populated for proper operation. If a memory bank is not used, it should be populated with a memory continuity module.
  • Page 64 Installing the Board The RDRAM RIMMs must conform to the following: 2.5V only, single-sided or double-sided (PC-600) RDRAM Serial Presence Detect (SPD) EEPROM 64-bit and 72-bit RIMMs Error Checking and Correction (ECC) or parity bit, with 72-bit RIMMs. Installation On an anti-static plane, place the board so that you are facing the RIMM sockets (the edge bracket must be located on the right).
  • Page 65 Technical Reference Manual 3.5. BUILDING A CPCI SYSTEM When building a CompactPCI system, a minimum requirement consists in a chassis, a CompactPCI backplane, a storage module, a power supply unit, and a ventilation system. The main AC power is drawn to the chassis components through an IEC power plug with a 2-stage filter, fuse holder and power switch.
  • Page 66 Installing the Board 3.5.1. Backplane An entry-level backplane is provided by Kontron. It is referred to as cBP-08R. It features 8 CPCI slots (one PCI I/O segment), and includes J3-J5 I/O connectors on all slots. A 16-CPCI-slot backplane (cBP-16R) is also available from Kontron. It supports two PCI...
  • Page 67 Technical Reference Manual 3.5.2. Rear-Panel I/O This feature is intended to issue the I/O capabilities of the system processor to the rear of the enclosure using a Rear I/O Transition module (cTM80-STD2S). The Rear I/O Transition module gathers all the I/O signals of the CPU board and makes them easily accessible through standard headers and connectors located at the rear of enclosure.
  • Page 68 Installing the Board Rev. 3-23...
  • Page 69 The ventilation unit of the enclosure conforms to the global requirement of the system in fully loaded configuration. 3.5.6. Installing the Board into a Bay The cPCI-DXS64 is mechanical Eurocard form factor boards. It takes advantages of the IEEE1101.10 specifications that ensure a mechanical interchange capability between different plug-in elements in sub-racks.
  • Page 70 Color coded keys prevent inadvertent installation of a 5V peripheral/system board in a 3.3V slot. The cPCI-DXS64 is 3.3v only to support 66Mhz pci bus. It does support Yellow coding key. The PCI bus require to be keyed. Backplane connectors must always be keyed according to the signaling (VIO) level.
  • Page 71 Technical Reference Manual To engage the board’s connectors into the backplane connector, press simultaneously on the front plate. Fasten the module using the fellow-plate fixing screw to secure the module to the system chassis. To remove the module from the chassis, proceed as follows: Remove the front plate fixing screws.
  • Page 72 Installing the Board 3.6.1.3. Serial Port C Signal Pin Assignation Description DCD3# Data Carrier Detect RXD3 Receive Data DSR3# Data Set Ready TXD3 Transmit Data RTS3# Ready To Send CTS3# Clear To Send RI3# Ring Indicator DTR3# Data Terminal Ready 3.6.1.4.
  • Page 73 Technical Reference Manual 3.6.1.6. IR Serial Port B Signal Description Assignation COM2_IRRX IR receive data line (Serial Port B) COM2_IRTX IR transmit data line (Serial Port B) 3.6.1.7. Hot Swap HA (High Availability) signals Signal Pin Assignation Description Board Select, one of the shortest pins (the last to...
  • Page 74 Installing the Board 3.6.2.2. SCSI Interface Signal Pin Assignation Description E7, D7, C7, B7, A7, E6, SCSI Data – The SCSI data lines drive the ID during SD - 0-15 D6, C6, E2, D2, C2, B2, arbitration and selection, and command and data E8, D8, C8, B8 information as well as status and messages.
  • Page 75 Technical Reference Manual 3.6.2.3. Video Interface Signal Pin Assignation Description VSDA Video serial data line (video I2C) VSCL Video serial clock line (video I2C) HSYNC Horizontal sync line VSYNC Vertical sync line Analog Red video signal GREEN Analog Green video signal...
  • Page 76 Installing the Board 3.6.2.6. IDE 1 Interface Signal Pin Assignation Description IDE1_RST# Reset signal B20, E19, C19, A19, Sec. Disk Data – These signals are used to transfer D18, B18, E17, C17, SDD 0-15 D17, A18, C18, E18, data to or from the IDE device. B19, D19, A20, C20 Sec.
  • Page 77 Technical Reference Manual 3.6.3. J5 Signal Specification 3.6.3.1. IDE 0 Interface Signal Pin Assignation Description IDE0_RST# IDE0 Reset line IDE0_RST# IDE0 Reset line B4, E3, C3, A3, D2, B2, E1, C1, D1, A2, Prim. Disk Data – These signals are used to transfer...
  • Page 78 Installing the Board 3.6.3.2. USB 0 and 1 Interfaces Signal Pin Assignation Description USBD1-0 (+/-) B18, C18, D19, E19 USB Data – Differential data path for USB 0 and 1 ports USB Ground – Differential ground reference for USB 0 USBG 1-0 B19, D18 and 1 ports...
  • Page 79 Technical Reference Manual 3.6.3.4. Serial Port A Signal Pin Assignation Description DCD1# Data Carrier Detect RXD1 Receive Data DSR1# Data Set Ready TXD1 Transmit Data RTS1# Ready To Send CTS1# Clear To Send RI1# Ring Indicator DTR1# Data Terminal Ready 3.6.3.5.
  • Page 80 Installing the Board 3.6.3.6. Parallel Port Signal Pin Assignation Description SLCT Printer select Paper end BUSY Busy signal ACK# Acknowledge handshake PD 0-7 E17, C17, A17, D16, C16, B16, A16, E15 Parallel port data bus SLCTIN# Printer select Auto line feed INIT# Initiate output ERR#...
  • Page 81 Technical Reference Manual 3.6.3.8. Keyboard Interface Signal Pin Assignation Description KDATA Keyboard data KCLK Keyboard clock VCC-KBD Keyboard power 3.6.3.9. Mouse Interface Signal Pin Assignation Description MDATA Mouse data MCLK Mouse clock 3-36...
  • Page 82 SOFTWARE SETUP PHOENIX BIOS SETUP PROGRAM BOOT UTILITIES INSTALLING DRIVERS...
  • Page 83 The system BIOS (Basic Input Output System) provides an interface between the operating system and the hardware of the cPCI-DXS64 System processor. This board uses the Phoenix Setup program, a setup utility in flash memory that is accessed by pressing the <DELETE>...
  • Page 84 When you get the following message, hit <DELETE> key to enter SETUP PhoenixBIOS 4.0 Release 6.0 Copyright 1985-2000 Phoenix Technologies Ltd. All Rights Reserved KONTRONS INC cPCI-DXS64 BIOS Version 1.4 The main menu of the Phoenix BIOS CMOS Setup Utility appears on the screen. cPCI-DXS64 BIOS Version 1.03 Kontrons, Inc.
  • Page 85 Software Setups Whenever you are not sure about a certain setting, you may refer to the list of default values. The list of defaults is provided in the event that a value has been changed and one wishes to set this option to its original value. Loading the SETUP defaults will affect all the options in this screen (or all parameters if defaults are loaded from the Main Menu) and will reset options previously altered.
  • Page 86 Technical Reference Manual 4.1.2.1. The Legend Bar Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu. The chart on the following page describes the legend keys and their alternates: Function <F1>...
  • Page 87 Software Setups 4.1.2.3. The General Help Windows Pressing <F1> or <Alt-H> on any menu brings up the General Help window that describes the legend keys and their alternates: General Help Setup changes system behavior by modifying the BIOS configuration. Selecting incorrect values may cause system boot failure;...
  • Page 88 <End> displays the first and last page. Pressing <Enter> displays each page and then exits the window. 4.1.2.4. Main Menu Selection You can make the following selections on the Main Menu itself. Use the sub menus for other selections. Kontrons, Inc cPCI-DXS64 BIOS Version 1.03 Main Advanced Power Boot...
  • Page 89 Software Setups Main Menu Selection (continued) Feature Options Description Multi-Sector Transfers Choices : Disabled, 2,4,8, and 16 sectors Any selection except Disabled determines the number of sectors transferred per block. Standard is 1 sector per block. LBA Mode Control Choices : Disabled, Enabled Enabling LBA causes Logical Block Addressing to be used in place of Cylinders, heads, and...
  • Page 90 Technical Reference Manual Main Selection Menu (continued) Feature Options Description IDE Removable Same choices as CD-ROM Other ATAPI Same choices as CD-ROM Cylinders Set the number of cylinders Heads Set the number of heads. Choices are 1 to 16...
  • Page 91 Software Setups Main Menu Selection (continued) Feature Options Description Auto BIOS autodetects the hard disk installed None CD-ROM ATAPI Removable Type Primary Slave Same description as Primary Master (continued) IDE Removable User Auto Secondary Same as Primary Master Master Secondary Same as Primary Master Slave Enter the new Supervisor Password and Confirm it...
  • Page 92 Technical Reference Manual 4.1.2.5. Advanced Menu Selection You can make the following selections on the Advanced Menu. Use the sub menus for other selections. Kontrons, Inc. cPCI-DXS64 BIOS Version 1.03 Main Advanced Power Boot Exit Item Specific Help Installed OS...
  • Page 93 Software Setups Feature Options Description Other : Non PnP or ACPI OS. Other Win95 : PnP OS. Win95 Win98/Win2000 : ACPI OS. Installed O/S Win98 Select the operating system installed on your WinMe system, which you will use most commonly. Win2000 Note : An incorrect setting can cause some operating systems to display unexpected behavior.
  • Page 94 Technical Reference Manual Advanced Menu Selection (continued) Feature Options Description Onboard Ethernet 1 Disabled Enables / Disables the onboard Ethernet Controller Enabled controller.1 Onboard Ethernet 2 Disabled Enables / Disables the onboard Ethernet Controller Enabled controller 2 Onboard SCSI Disabled Enables / Disables the onboard SCSI controller.
  • Page 95 Software Setups Advanced Menu Selection (continued) Default, Minimum guaranteed time slice allotted for 20h, 40h, ICH Secondary bus master in units of PCI bus clocks. 60h, 80h, Latency timer A0h, C0h or Default value equals 0h (No Latency). Multi Transaction Timer defines the minimum guaranteed time slice allotted for Default, PCI initiator to perform...
  • Page 96 Technical Reference Manual Advanced Menu Selection (continued) Feature Options Description L1 Cache Enabled Sets the state of L1 memory cache. Memory Disabled L2 Cache Enabled Sets the state of L2 memory cache. Memory Disabled Uncached Cache System Controls caching of system B0S area.
  • Page 97 Software Setups Advanced Menu Selection (continued) Feature Options Description Cache CC00-CFFF Cache D000-D3FF Cache D400-D7FF Cache D800-DBFF Cache DC00-DFFF Cache Memory Same as above Cache E000-E3FF Cache E400- E7FF Cache E800-EBFF Cache EC00- EFFF Configure serial port A using options: Disabled : No configuration Disabled Enabled : User configuration...
  • Page 98 Technical Reference Manual Advanced Menu Selection (continued) Feature Options Description Configure parallel port using options : Disabled : No configuration Enabled : User configuration Disabled When enabled, set the Base I/O Enabled address. Auto Auto: BIOS chooses OS Controlled...
  • Page 99 Software Setups Advanced Menu Selection (continued) Feature Options Description 4, 8, 16, 32, 64, Select the size of the Graphics Aperture for Graphics Aperture 128 or 256Mb the AGP video device. If enabled, turns system RAM off to allocate Disabled this address space to an optional card.
  • Page 100 Technical Reference Manual Advanced Menu Selection (continued) Enables the Watchdog circuit when the Watchdog Timer Disabled, Enabled POST is running. Enables the Watchdog circuit after the POST sequence. Watchdog After The BIOS will hook the Timer Tick Disabled, Enabled...
  • Page 101 Software Setups 4.1.2.6. Power Menu Selection Feature Options Description Enables/Disables the Intelligent System Disabled Monitor device. When enabled, the system Intelligent System will monitor some system states such as Monitoring Enabled temperature and power supplies. Enables/Disables generation Disabled interrupts when an event occurs. This must Interrupt Generation be set to DISABLED when programs such Enabled...
  • Page 102 Technical Reference Manual Power Menu Selection (continued) Description Feature Options Present LoLimit HiLimit ----- ----- Vcore CPU 1 1.65V ----- ----- Vcore CPU 2 1.66V ----- ----- Vin 2.5 2.48 All items on this menu cannot be ----- ----- Vin 3.3...
  • Page 103 Software Setups 4.1.2.7. Boot Menu Selection Feature Options Description Hard Drive Keys used to view or configure devices: Bootable Add-in Cards <Enter> expands or collapses devices with a + or – Primary Master <Ctrl+Enter> expands all Removable Devices <Shift + 1> enables or disables a device Legacy Floppy Drives <+>...
  • Page 104 Technical Reference Manual 4.2. BOOT UTILITIES Phoenix Boot Utilities are : Phoenix QuietBoot™ Phoenix MultiBoot™ Phoenix QuietBoot displays a graphic illustration rather than the traditional POST messages while keeping you informed of diagnostic problems. Phoenix MultiBoot is a boot screen that displays a selection of boot devices from which you can boot your operating system.
  • Page 105 Software Setups 4.2.1.2. Press <Del> Pressing < Del > at any time during POST switches to the POST screen (if not already displayed) and enter Setup. 4.2.1.3. POST Error Whenever POST detects a non-fatal error, QuietBoot switches to the POST screen and displays the errors.
  • Page 106 Technical Reference Manual 4.3. INSTALLING DRIVERS 4.3.1. Video Drivers Various drivers are provided for different operating systems and software. To install a driver, refer to the Setup program located on the CD-ROM (provided with your board). 4.3.2. Ethernet Drivers Various drivers are provided for different operating systems and software.
  • Page 107 Software Setups 4.4. VT100 MODE The VT100 operating mode allows remote setups of the board. This configuration requires a remote terminal that must be connected to the board through a serial communication link. 4.4.1. Requirements The terminal should emulate a VT100 or ANSI terminal. Terminal emulation programs such ©...
  • Page 108 Technical Reference Manual Console Redirection provided by Phoenix based BIOS offers various escape sequences to emulate keyboard function keys. The following table lists the escape sequences available. Escape sequence Function Escape sequence Function Esc Del Warm Reset Esc [ 6 4 ~...
  • Page 109 APPENDICES MEMORY & I/O MAPS INTERRUPT LINES BOARD DIAGRAMS CONNECTOR PINOUTS BIOS SETUP ERROR CODES BIOS UPDATE & EMERGENCY PROCEDURE GETTING HELP & RMA...
  • Page 110 A. MEMORY & I/O MAPS EMORY APPING FFFFFh System BIOS E0000h 1MB to top of DRAM Optional ROM (Free) LAN BIOS if activated (~30KB) See Note 1 See Note 2 SCSI BIOS (18KB at runtime) Optional ROM (Free) C 000h Video BIOS C0000h 100000h...
  • Page 111 Technical Reference Manual I/O M APPING Address Optional Optional Optional Function Address Address Address 000-01F DMA Controller 1 020-03F Interrupt Controller 1 040-05F Timer 060-06F Keyboard 070-07F Real-time clock 080-09F DMA Page Register 0A0-0BF Interrupt Controller 2 0C0-0DF DMA Controller 2...
  • Page 112 1 Available lines service on board and external PCI/ISA PnP devices or a Legacy ISA device. DMA C HANNELS The cPCI-DXS64 integrates the functionality of two 8237 DMA controllers. Eight DMA channels are available. According to Plug and Play standards, the system BIOS automatically allocates DMA Channel 1 or 3 for the parallel port's ECP mode.
  • Page 113 C. BOARD DIAGRAMS EVICES URFACE OUNT...
  • Page 114 Technical Reference Manual BOTTOM DEVICE SURFACE MOUNT...
  • Page 115 Board Specifications OUNTING OLES...
  • Page 116 Technical Reference Manual ONNECTOR OLES...
  • Page 117 D. CONNECTOR PINOUTS PCI- DXS64 C ONNECTORS AND EADERS DXS64 Connector J14 CPCI Bus connector CPCI Bus connector CPCI I/O connector CPCI I/O connector CPCI I/O connector J6, J16 CPU socket, PGA370 J7, J15 Not used J8, J9, J11, J12 RIMM sockets CRT VGA Connector (Front panel configuration only) Mezzanine...
  • Page 118 Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E VCC5E -12VE +12VE VCCE VCCE INTA# INTB# INTC# VCCE INTD# IPMB0_PW HEALTHY# VI/O INTP INTS BRSVP1A5 BRSVP1B5 RST# GNT0# REQ0# VCC3E CLK0 AD31 AD30...
  • Page 119 Connector Pinouts PCI B ROW A ROW B ROW C ROW D ROW E REQ1# GNT1# REQ2# S_CLK1 S_CLK2 S_CLK3 SYSEN# GNT2# REQ3# S_CLK4 GNT3# REQ4# GNT4# BRSV CBE7# CBE6# V I/O CBE5# V I/O CBE4# PAR64 AD63 AD62 AD61 AD60 AD59 V I/O...
  • Page 120 Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E SCSI:D11+ SCSI:I/O+ SCSI:D9+ SCSI:DIFFSENS SCSI:D10+ SCSI:C/D+ SCSI:SEL+ SPEEDLED0 LINKLED_0 ACTLED0 LINKLED_1 SPEEDLED1 ACTLED_1 LAN1 :ETX+ LAN1 :ETX- LAN1 :ERX+ LAN1 :ERX- WR_80# +12V +12V...
  • Page 121 Connector Pinouts PCI B ROW A ROW B ROW C ROW D ROW E I2C-CLK I2C-DATA EXTFAN0FAIL# EXTFAN1FAIL# SM-BYPASS# SCSI:D10- SCSI:D9- SCSI:D8- SCSI:D11- SCSI:I/O- SCSI:REQ- SCSI:C/D- SCSI:SEL- SCSI:MSG- SCSI:RST- SCSI:ACK- SCSI:BSY- SCSI:BSY+ SCSI:ATN- SCSI:TERMPW SCSI:TERMPW SCSI:ACK+ SCSI:DPO+ SCSI:ATN+ SCSI:DP0- SCSI:D7- SCSI:D6- SCSI:D5- SCSI:D4-...
  • Page 122 Technical Reference Manual PCI B ROW A ROW B ROW C ROW D ROW E IDE0:RST# IDE0:RST# IDE0:D7 IDE0:D8 IDE0:D6 IDE0:D9 IDE0:D5 IDE0:D10 IDE0:D4 IDE0:D11 IDE0:D3 IDE0:D12 IDE0:D2 IDE0:D13 IDE0:D1 IDE0:D14 IDE0:D0 USB1:GND IDE0 :D15 IDE0 :IRQ14 IDE0:REQ IDE0:I0RDY...
  • Page 123 Connector Pinouts J10, V (VGA) IDEO Top View Signal Signal Signal Analog GND Not Connected GREEN Analog GND SDATA BLUE Analog GND HSYNC Not Connected Not Connected VSYNC SCLK J13, M (SCSI) EZZANINE Pin Number Top View Pin Number Signal Signal SD-12 SD+12...
  • Page 124 Technical Reference Manual J14, S 1 - RS-232 ERIAL Pin Number Pin Number Top View Signal Signal D.10 J17, C OMPACT LASH Top View Pin Number Pin Number Signal Signal DD11 DD12 DD03 DD13 DD04 DD14 DD05 DD15 DD06...
  • Page 125 Connector Pinouts D.11 J18, USB C ONNECTORS LATE Signal Front View DATA- DATA+ D.12 J19, M (PCI) EZZANINE Pin Number Top View Pin Number Signal Signal P64_IRQ7 P64_IRQ9 P64_IRQ8 P64_IRQ6 P64_IRQ5 P64_IRQ4 PCIRST# IDEACTP# PDCS#1 PDCS#3 PDA0 PDA2 PDA1 P66DETECT IDE_IRQ14 SERR# PDDACK#...
  • Page 126 Technical Reference Manual D.13 J20, M (64-BIT/66MHZ) EZZANINE Top View Pin Number Pin Number Signal Signal REQ64# ACK64# C/BE#7 C/BE#4 C/BE#5 C/BE#6 PAR64 AD63 AD61 AD62 AD59 AD60 AD58 AD57 AD56 AD55 AD54 AD53 AD52 AD51 AD49 AD50 AD47...
  • Page 127 Connector Pinouts D.14 J23, M (64-BIT/66MHZ) EZZANINE Top View Pin Number Pin Number Signal Signal AD30 CLKOUT2 ACK64# C/BE#4 CLKOUT3 C/BE#6 AD63 CLKOUT1 AD61 AD59 AD20 AD18 AD57 AD22 AD55 AD16 AD53 FRAME# AD51 TRDY# AD49 STOP# AD47 AD15 AD45 AD43 AD13 AD41...
  • Page 128 Technical Reference Manual D.16 J22, MEZZANINE CONNECTOR Top View Pin Number Pin Number Signal Signal EN+GLAN MS_PCI_RST#8 IPMB0_SDA MS_BD_SEL#8 MS_HEALTHY#8 MS_HEALTHY#7 MS_HEALTHY#4 MS_PCI_RST#7 MS_PCI_RST#4 MS_BD_SEL#7 MS_BD_SEL#4 MS_HEALTHY#6 MS_HEALTHY#3 MS_PCI_RST#6 MS_PCI_RST#3 MS_BD_SEL#6 MS_BD_SEL#3 P64REQ#2 VCC3 P64GNT#2 P64GNT#1 VCC3 VCC3 P64GNT#3...
  • Page 129 Connector Pinouts D.18 J25, H WITCH Top View Signal VCC3E SW_OPEN# D.19 SW1 – R ESET WITCH Side View Signal RESET# D.20 SW2 – NMI S WITCH Signal Side View NMI# D.21 BT1, CMOS B ATTERY ACKUP ONNECTOR Signal Front View Battery (+) Battery (-) D-13...
  • Page 130 E. BIOS SETUP ERROR CODES POST B Recoverable POST Errors Whenever a recoverable error occurs during POST, Phoenix BIOS displays an error message describing the problem. Phoenix BIOS also issues a beep code (one long tone followed by two short tones) during POST if the video configuration fails (no card installed or faulty) or if an external ROM module does not properly checksum to zero.
  • Page 131 Technical Reference Manual POST M ESSAGES During the Power On Self Test (POST), if the BIOS detects an error requiring you to do something to fix, it will either sound a beep code or display a message. If a message is displayed, it will be accompanied by: “PRESS F1 TO CONTINUE, DEL TO ENTER SETUP”.
  • Page 132 BIOS Setup Error Codes OFFENDING SEGMENT This message is used in conjunction with the I/O CHANNEL CHECK and RAM PARITY ERROR messages when the segment that has caused the problem cannot be isolated. PRESS F1 TO DISABLE NMI, F2 TO REBOOT When BIOS detects a Non Maskable Interrupt condition, this will allow you to disable the NMI and continue to boot, or you can reboot the system with the NMI enabled.
  • Page 133 F. BIOS UPDATE & EMERGENCY PROCEDURE For BIOS update, see the procedure included in our FAQ document than can be found on the FAQ section of the FTP site under FAQ # KC_0028 at location: ftp://ftp.kontron.ca/Support/Support_FAQ - Questions & Answers/ EMERGENCY PROCEDURE Symptoms: •...
  • Page 134 G. GETTING HELP At Kontron, we take great pride in our customer’s successes. We strongly believe in providing full support at all stages of your product development. If at any time you encounter difficulties with your application or with any of our...
  • Page 135 H. Returning Defective Merchandise If your Kontron product malfunctions, please do the following before returning any merchandise: 1) Call our Technical Support department in Canada at (450) 437-5682. Make certain you have the following at hand: • The Kontron Invoice number •...
  • Page 136 : ___________________ Postal/Zip Code: ______________ Phone Number : __________________ Extension : ___________________ Fax Number : __________________ P.O. # Serial Number Failure or Problem Description (if not under warranty) Fax this form to Kontron’s Technical Support department in Canada at (450) 437-8053...