Fast Wake-Up - Holtek HT45F23A Manual

HT45F23A/HT45F24A
TinyPower Flash MCU with OPA & Comparators
TM
IDLEN: IDLE Mode control
Bit 1
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
devices will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the devices will enter the SLEEP Mode when a HALT
instruction is executed.
Bit 0 HLCLK: system clock selection
0: f
1: f
This bit is used to select if the f
the system clock. When the bit is high the f
f /2~f
H
to the f

Fast Wake-up

To minimise power consumption the devices can enter the SLEEP or IDLE0 Mode, where the
system clock source to the devices will be stopped. However when the devices are woken up again,
it can take a considerable time for the original system oscillator to restart, stabilise and allow normal
operation to resume. To ensure the devices are up and running as fast as possible a Fast Wake-
up function is provided, which allows f
temporary clock to first drive the system until the original system oscillator has stabilised. As the
clock source for the Fast Wake-up function is f
the SLEEP1 and IDLE0 modes. When the devices are woken up from the SLEEP0 mode, the Fast
Wake-up function has no effect because the f
function is controlled using the FSTEN bit in the SMOD register.
If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up
function is enabled, then it will take one to two t
the system to wake-up. The system will then initially run under the f
HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will
switch over to operating from the HXT oscillator.
If the ERC, EC or HIRC oscillators or LIRC oscillator is used as the system oscillator then it will
take 15~16 clock cycles of the ERC, EC or HIRC or 1~2 cycles of the LIRC to wake up the system
from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases.
System FSTEN
Oscillator Bit
HXT
ERC
EC
HIRC
LIRC
LXT
Note that if the Watchdog Timer is disabled, which means that the LXT and LIRC are all both off, then
there will be no Fast Wake-up function available when the devices wake-up from the SLEEP0 Mode.
Rev. 1.40
/2 ~ f /64 or f
H H L
H
/64 or f clock will be selected. When system clock switches from the f
H L
clock and the f clock will be automatically switched off to conserve power.
L H
, namely either the LXT or LIRC oscillator, to act as a
SUB
SUB
Wake-up Time Wake-up Time
(SLEEP0 Mode) (SLEEP1 Mode)
0 1024 HXT cycles 1024 HXT cycles
1~2 f
(System runs with f
1 1024 HXT cycles
HXT cycles and then switches over to
run with the HXT clock)
X 15~16 ERC cycles 15~16 ERC cycles
X 15~16 EC cycles 15~16 EC cycles
X 15~16 HIRC cycles 15~16 HIRC cycles
X 1~2 LIRC cycles 1~2 LIRC cycles
X 1024 LXT cycles 1024 LXT cycles
Wake-Up Times
45
clock or the f /2 ~ f /64 or f
H H H
clock will be selected and if low the
H
, the Fast Wake-up function is only available in
SUB
clock is stopped. The Fast Wake-up enable/disable
clock cycles of the LIRC or LXT oscillator for
SUB
clock source until 1024
SUB
Wake-up Time
(IDLE0 Mode)
cycles
SUB
first for 1024
SUB
clock is used as
L
clock
H
Wake-up Time
(IDLE1 Mode)
1~2 HXT cycles
1~2 HXT cycles
1~2 ERC cycles
1~2 EC cycles
1~2 HIRC cycles
1~2 LIRC cycles
1~2 LXT cycles
March 29, 2019