Watchdog Timer; Watchdog Time� Clock So; Watchdog Time� Cont�Ol Registe - Holtek BS83B24C Manual

BS83B24C/BS83C40C
Touch Flash MCU

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal RC oscillator, f
oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary
with V , temperature and process variations. The Watchdog Timer source clock is then subdivided
DD
by a ratio of 2 to 2
8
bits in the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable and reset MCU
operation.
• WDTC Register
Bit 7
Name WE4
R/W R/W
POR 0
Bit 7~3 WE4~WE0: WDT function software control
10101/01010: Enable
Others: Reset MCU
When these bits are changed by the environmental noise or software setting to reset
the microcontroller, the reset operation will be activated after a delay time, t
the WRF bit in the RSTFC register will be set high.
Bit 2~0 WS2~WS0: WDT time-out period selection
000: 2
001: 2
010: 2
011: 2
100: 2
101: 2
110: 2
111: 2
These three bits determine the division ratio of the watchdog timer source clock,
which in turn determines the time-out period.
• RSTFC Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
RSTF: Reset Control Register Software Reset Flag
Bit 3
Described elsewhere
LVRF: LVR function reset flag
Bit 2
Described elsewhere
Bit 1 LRF: LVR Control Register Software Reset Flag
Described elsewhere
Rev. 1.00
to give longer timeouts, the actual value being chosen using the WS2~WS0
18
6 5 4
WE3 WE� WE1
R/W R/W R/W
1 0 1
/f
8
LIRC
/f
10
LIRC
/f
12
LIRC
/f
14
LIRC
/f
15
LIRC
/f
16
LIRC
/f
17
LIRC
/f
18
LIRC
6 5 4
— — —
— — —
— — —
55
. The LIRC internal
LIRC
3 2 1
WE0 WS� WS1
R/W R/W R/W
0 0 1
3 2 1
RST� LVR� LR�
R/W R/W R/W
0 x 0
"x": Unknown
�e���a�� 0�� �01�
0
WS0
R/W
1
, and
SRESET
0
WR�
R/W
0