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QB-78F1030
4.1.7
Absolute maximum rating of p62 pin
The absolute maximum rating of the P62 pin differs between the target device and emulator.
IECUBE may be damaged if a voltage greater than 5.5 V is applied.
Target device
IECUBE
4.1.8
FLMD0 pin
The processing for the FLMD0 pin differs from that of the target device.
Item
Target device
IECUBE
4.1.9
Power-on-clear (POC) voltage value
The power-on-clear (POC) voltage value differs from that of the target device.
Target device
IECUBE
4.1.10 TTL input buffer characteristics
If the port input mode register (PIM) is used to set the input of a pin that can be set for the TTL buffer to the TTL level,
the high-level input voltage characteristics differ between the target device and emulator. See Table 4-6 for details.
The following pins can be set for the TTL buffer.
Target pins: P03, P04, P10, P11, P142, P143
Target device
IECUBE
Note Use CMOS input if V
R20UT0289JJ0100 Rev. 1.00
Sep 30, 2010
Table 4-3. Absolute maximum rating of P62 pin
Item
6.5 V
5.5 V
Table 4-4. FLMD0 Pin Processing
Protection resistance: 4.5 kΩ (TYP.)
Pull-up/pull-down resistors: 10 kΩ (MIN.), 20 kΩ (TYP.), 100 kΩ (MAX.)
Protection resistance: 4.7 kΩ (TYP.)
Pull-up/pull-down resistors: 29 kΩ (MIN.), 30 kΩ (TYP.), 32 kΩ (MAX.)
Table 4-5. Power-on-clear (POC) voltage value
Item
VPOR
1.52 V
VPDR
1.50 V
VPOR
VPDR
Table 4-6. High-Level Input Voltage Characteristics
Item
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
1.8 V ≤ V
Note
is 2.0 V or less.
DD
Absolute maximum rating of P62 pin
FLMD0 Pin Processing
MIN.
TYP.
1.61 V
1.59 V
−
1.65 V
−
1.55 V
Conditions
≤ 5.5 V
DD
< 4.0 V
DD
< 2.7 V
DD
≤ 5.5 V
DD
CHAPTER 4 CAUTIONS
MAX.
1.70 V
1.68 V
−
−
MIN
2.2 V
2.0 V
1.6 V
2.0 V
Page 27 of 28
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