Generation Of Interrupt - Epson S1C6S3N2 Technical Manual

Table 4.2.1
Interrupt factors
S1C6S3N2 TECHNICAL SOFTWARE
4.2

Generation of Interrupt

Interrupt Factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Stopwatch counter
1 Hz falling edge
Stopwatch counter
10 Hz falling edge
Input data (K00–K03)
Change from match to mismatch
of differential register data
and port register data
Input data (K10)
Rising or falling edge
The CPU operation is interrupted when any of the conditions
below sets an interrupt factor flag to "1".
• The corresponding interrupt mask register is "1" (enabled)
• The interrupt flag is "1" (EI)
The interrupt flag is set to "1" depending on the correspond-
ing interrupt factor.
The interrupt factor flag is a read-only register, and is reset
to "0" when the register data is read out.
Note • Even when the interrupt mask registers (ETI, EISWIT) are set to
"0", the interrupt factor flags (TI, SWIT) of the clock timer and
stopwatch counter can be set when the timing conditions are
established.
• Reading of interrupt factor flags is available at EI, but be careful
in the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to "1", an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
CHAPTER 4: INTERRUPT AND HALT
T2Hz ETI2
T8Hz ETI8
T32Hz ETI32
SWT1Hz EISWIT1
SWT10Hz EISWIT0
K0 EIK03
EIK02
EIK01
EIK00
K1 EIK10
EPSON
Interrupt Mask Interrupt
Register Factor Flag
(078H•D2) TI2
(078H•D1) TI8
(078H•D0) TI32
(076H•D1) SWIT1
(076H•D0) SWIT0
(075H•D3) IK0
(075H•D2)
(075H•D1)
(075H•D0)
(077H•D2) IK1
(079H•D2)
(079H•D1)
(079H•D0)
(07AH•D1)
(07AH•D0)
(07AH•D2)
(07AH•D3)
II-15