Epson S1C6S3N2 Technical Manual page 210

CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer)
(2) Operating interrupt mask register by separate bits
Specifications
Program
(3) Processing after timer interrupt generated
Specifications
Table 5.6.3
Order of priority of interrupts
in program example
Program
;
;
;
YTIB
;
;
II-64
This program enables the timer 8 Hz interrupt only, and
then masks the timer 32 Hz interrupt.
DI
LD
OR
AND
EI
This program stores the register when an interrupt is gener-
ated, and when the interrupt processing is completed it
recovers the register data and returns to the main routine.
The order of priority for the interrupts is set as shown in the
table below, interrupt nesting is disabled, and processing
proceeds in descending order of priority. The interrupt
processing routine is called with CALL instruction and
processed.
Order of Priority
ORG 104H
JP INTI
EQU H
EPSON
; Disable interrupt
X,78H ;
Enable timer 8 Hz interrupt
MX,0010B ;
MX,1110B ; Mask timer 32 Hz interrupt
;
Enable interrupt
Interrupt Factor
1 Clock timer 32 Hz
2 Clock timer 8 Hz
3 Clock timer 2 Hz
;
Interrupt vector address of timer interrupt
;
Go to "INTI" if timer interrupt is generated
; Buffer address of timer interrupt factor flags
S1C6S3N2 TECHNICAL SOFTWARE