Epson S1C6S3N2 Technical Manual page 176

CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Program
XTISF
YFTM
;
;
TI2:
;
;
TI2RT: RET
TI21:
;
Timing chart of SVD operation
Fig. 5.3.2
Timing chart of
SVD operation
II-30
EQU 0001B
EQU H
LD X,YFTM
FAN MX,XTISF
JP NZ,TI21
OR MX,XTISF
LD X,76H
OR MX,0100B
AND MX,1011B
FAN MX,0100B
JP Z,TI2RT
CALL DSBLD
AND MX,XTISF XOR 0FH ;
CALL CK
RET
The address for the timing flag set FTM can be set anywhere
in RAM.
This routine assumes that a timer subroutine has been
prepared separately to make 1 second the unit for the rou-
tine "basic timer 'CK'".
(See page 63, "Example of using timer interrupt" for how to
make "basic timer 'CK'".)
Source voltage
1 sec
BLS register
BLD register
HLMOD circuit
SVD circuit
;
0.5-sec flag (TISF)
; Address for timing flag set
; TISF = "0" or "1"?
;
;
; TISF = "0": Set the TIS flag
; Detect: BLS ON
;
;
; If result is "1" (low voltage)
;
; then
;
Return to parent routine
TISF = "1": Reset the TIS flag
;
Execute the basic timer "CK"
;
Return to parent routine
0.5 sec
EPSON
BLS OFF
execute display routine "DSBLD"
Criteria voltage
(1.2 V)
S1C6S3N2 TECHNICAL SOFTWARE