4.1 Control Of Interrupt And Halt - Epson S1C6S3N2 Technical Manual

Cmos 4-bit single chip microcomputer
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4.1 Control of Interrupt and HALT

Table 4.1.1(a) I/O data memory map (interrupt 1)
Address
D3
DFK03
074H
EIK03
075H
HLMOD
R/W
076H
0
R
077H
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Constantly "0" when being read
S1C6S3N2 TECHNICAL SOFTWARE
Register
D2
D1
D0
Name
DFK02
DFK01
DFK00
DFK03
R/W
DFK02
DFK01
DFK00
EIK02
EIK01
EIK00
EIK03
R/W
EIK02
EIK01
EIK00
BLD
EISWIT1 EISWIT0
HLMOD
BLS
BLD
R
R/W
BLS
W
EISWIT1
EISWIT0
EIK10
DFK10
K10
EIK10
R/W
R
DFK10
K10
SR
*1
1
0
0
Falling
Rising
0
Falling
Rising
0
Falling
Rising
0
Falling
Rising
0
Enable
Mask
0
Enable
Mask
0
Enable
Mask
0
Enable
Mask
Heavy
0
Normal
load
Normal
0
Low voltage
ON
OFF
0
0
Enable
Mask
0
Enable
Mask
*2
0
0
Enable
Mask
0
Falling
Rising
*2
High
Low
EPSON
CHAPTER 4: INTERRUPT AND HALT
Comment
Differential register
(K00–K03)
Interrupt mask register
(K00–K03)
Heavy load protection mode register
SVD evaluation data
SVD ON/OFF
Interrupt mask register
(stopwatch 1 Hz)
Interrupt mask register
(stopwatch 10 Hz)
Unused
Interrupt mask register (K10)
Differential register (K10)
Input port (K10)
II-13

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