Control Of Lcd Driver - Epson S1C6S3N2 Technical Manual

Control of LCD driver

Table 4.7.2 Control bits of LCD driver
Address
D3
CSDC
078H
*1 Initial value at the time of initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Constantly "0" when being read
Address Low
Page High
4 or C
0 5 or D
6 or E
Fig. 4.7.8
Segment data memory map
S1C6S3N2 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Table 4.7.2 shows the LCD driver's control bits and their
addresses. Figure 4.7.8 shows the segment data memory
map.
Register
D2 D1 D0 Name
ETI2 ETI8 ETI32 CSDC
R/W
ETI2
ETI8
ETI32
0 1 2 3
Segment data memory (38 words x 4 bits)
SR *1 1 0
0 Dynamic ALL OFF
0 Enable Mask
0 Enable Mask
0 Enable Mask
4 5 6 7 8
40H–6FH = R/W
C0H–EFH = W
EPSON
Comment
LCD drive switch
Interrupt mask register
(clock timer 2 Hz)
Interrupt mask register
(clock timer 8 Hz)
Interrupt mask register
(clock timer 32 Hz)
9 A B C D E F
I-59