Segger J-Link User Manual page 159

Jtag emulators for arm cores
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Parameter
Tsh
Thh
Tsl
Thl
Table 8.7: Clock frequency
The diagram below shows the TRACECLK frequencies and the setup and hold timing
of the trace signals with respect to TRACECLK.
Full
TRACECLK
DATA
Half-rate
TRACECLK
Note:
J-Trace supports half-rate clocking mode. Data is output on each edge of
the TRACECLK signal and TRACECLK (max) <= 100MHz. For half-rate clocking, the
setup and hold times at the JTAG+Trace connector must be observed.
J-Link / J-Trace (UM08001)
Min.
2.5ns
1.5ns
2.5ns
1.5ns
Tch
Tsh
Thh
Max.
-
Data setup high
-
Data hold high
-
Data setup low
-
Data hold low
Tperiod
Tcl
Tsl
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
Explanation
Thl
157

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