Segger J-Link User Manual page 170

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Exit1-DR
Temporary controller state.
Pause-DR
The shifting of the test data register between TDI and TDO is temporarily halted.
Exit2-DR
Temporary controller state. Allows to either go back into Shift-DR state or go on to
Update-DR.
Update-DR
Data contained in the currently selected data register is loaded into a latched parallel
output (for registers that have such a latch). The parallel latch prevents changes at
the parallel output of these registers from occurring during the shifting process.
Capture-IR
Instructions may be loaded in parallel into the instruction register.
Shift-IR
The instruction register shifts the values in the instruction register towards TDO with
each clock.
Exit1-IR
Temporary controller state.
Pause-IR
Wait state that temporarily halts the instruction shifting.
Exit2-IR
Temporary controller state. Allows to either go back into Shift-IR state or go on to
Update-IR.
Update-IR
The values contained in the instruction register are loaded into a latched parallel out-
put from the shift-register path. Once latched, this new instruction becomes the cur-
rent one. The parallel latch prevents changes at the parallel output of the instruction
register from occurring during the shifting process.
J-Link / J-Trace (UM08001)
CHAPTER 9
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
Background information