Segger J-Link User Manual page 151

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They
should also be connected to GND in the target system.
8.1.1.1 Target board design
We strongly advise following the recommendations given by the chip manufacturer.
These recommendations are normally in line with the recommendations given in the
table Pinout for JTAG on page 148. In case of doubt you should follow the recommen-
dations given by the semiconductor manufacturer.
You may take any female header following the specifications of DIN 41651.
For example:
Harting
Molex
Tyco Electronics
JTAG connector
J-Link
* NTRST and RTCK may not be available on some CPUs.
** Optional to supply the target board from J-Link.
8.1.1.2 Pull-up/pull-down resistors
Unless otherwise specified by developer's manual, pull-ups/pull-downs are recom-
mended to be between 2.2 kOhms and 47 kOhms.
J-Link / J-Trace (UM08001)
part-no. 09185206803
part-no. 90635-1202
part-no. 2-215882-0
Typical target connection for JTAG
19**
5V supply
1
VTref
3*
nTRST
5
TDI
7
TMS
9
TCK
11*
RTCK
13
TDO
15
RESET
20
GND
Target board
Voltage
19
Regulator
1
3
nTRST
5
TDI
7
TMS
9
TCK
11
RTCK
13
TDO
15
nRST
20
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
149
VCC
VCC
CPU
GND