Assignment Of Trace Information Pins Between Etm Architecture Versions; Trace Signals - Segger J-Link User Manual

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8.2.3 Assignment of trace information pins between ETM
architecture versions
The following table show different names for the trace signals depending on the ETM
architecture version.
Trace signal
Trace signal 1
Trace signal 2
Trace signal 3
Trace signal 4
Trace signal 5
Trace signal 6
Trace signal 7
Trace signal 8
Trace signal 9
Trace signal 10
Trace signal 11
Trace signal 12
Trace signal 13
Trace signal 14
Trace signal 15
Trace signal 16
Trace signal 17
Trace signal 18
Trace signal 19
Trace signal 20
Table 8.6: Assignment of trace information pins between ETM architecture versions
8.2.4

Trace signals

Data transfer is synchronized by TRACECLK.
8.2.4.1 Signal levels
The maximum capacitance presented by J-Trace at the trace port connector,
including the connector and interfacing logic, is less than 6pF. The trace port lines
have a matched impedance of 50.
The J-Trace unit will operate with a target board that has a supply voltage range of
3.0V-3.6V.
8.2.4.2 Clock frequency
For capturing trace port signals synchronous to TRACECLK, J-Trace supports
a TRACECLK frequency of up to 200MHz. The following table shows the TRACECLK
frequencies and the setup and hold timing of the trace signals with respect to TRACE-
CLK.
Parameter
Tperiod
Fmax
Tch
Tcl
Table 8.7: Clock frequency
J-Link / J-Trace (UM08001)
CHAPTER 8
ETMv1
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
TRACESYNC
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
Min. Max.
5ns 1000ns
1MHz 200MHz
2.5ns -
2.5ns -
Target interfaces and adapters
ETMv2
PIPESTAT[0]
PIPESTAT[1]
PIPESTAT[2]
PIPESTAT[3]
TRACEPKT[0]
TRACEPKT[1]
TRACEPKT[2]
TRACEPKT[3]
TRACEPKT[4]
TRACEPKT[5]
TRACEPKT[6]
TRACEPKT[7]
TRACEPKT[8]
TRACEPKT[9]
TRACEPKT[10]
TRACEPKT[11]
TRACEPKT[12]
TRACEPKT[13]
TRACEPKT[14]
TRACEPKT[15]
Explanation
Clock period
Maximum trace frequency
High pulse width
Low pulse width
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
ETMv3
TRACEDATA[0]
TRACECTL
Logic 1
Logic 0
Logic 0
TRACEDATA[1]
TRACEDATA[2]
TRACEDATA[3]
TRACEDATA[4]
TRACEDATA[5]
TRACEDATA[6]
TRACEDATA[7]
TRACEDATA[8]
TRACEDATA[9]
TRACEDATA[10]
TRACEDATA[11]
TRACEDATA[12]
TRACEDATA[13]
TRACEDATA[14]
TRACEDATA[15]