The Arm Core; Processor Modes; Registers Of The Cpu Core - Segger J-Link User Manual

9.2

The ARM core

The ARM7 family is a range of low-power 32-bit RISC microprocessor cores. Offering
up to 130MIPs (Dhrystone2.1), the ARM7 family incorporates the Thumb 16-bit
instruction set. The family consists of the ARM7TDMI, ARM7TDMI-S and ARM7EJ-S
processor cores and the ARM720T cached processor macrocell.
The ARM9 family is built around the ARM9TDMI processor core and incorporates the
16-bit Thumb instruction set. The ARM9 Thumb family includes the ARM920T and
ARM922T cached processor macrocells.
9.2.1

Processor modes

The ARM architecture supports seven processor modes.
Processor mode
User
System
Supervisor
Abort
Undefined
Interrupt
Fast inter-
rupt
Table 9.2: ARM processor modes
9.2.2

Registers of the CPU core

The CPU core has the following registers:
User/
System
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
PC
CPSR
Table 9.3: Registers of the ARM core
= indicates that the normal register used by User or System mode has been
replaced by an alternative register specific to the exception mode.
J-Link / J-Trace (UM08001)
usr Normal program execution mode.
sys Runs privileged operating system tasks.
svc A protected mode for the operating system.
abt Implements virtual memory and/or memory protection.
und Supports software emulation of hardware coprocessors.
irq Used for general-purpose interrupt handling.
fiq Supports a high-speed data transfer or channel process.flash
Supervisor Abort
R13_svc R13_abt
R14_svc R14_abt
SPSR_svc SPSR_abt
Description
Undefined Interrupt
R13_und R13_irq
R14_und R14_irq
SPSR_und SPSR_irq
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
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Fast
interrupt
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
SPSR_fiq