Segger J-Link User Manual page 14

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8.2.3 Assignment of trace information pins between ETM architecture versions .......156
8.2.4 Trace signals .........................................................................................156
8.3 19-pin JTAG/SWD and Trace connector .....................................................158
8.3.1 Target power supply ...............................................................................159
8.4 Adapters ...............................................................................................160
8.4.1 JTAG isolator .........................................................................................160
8.4.2 JTAG 14 pin adapter ...............................................................................161
8.4.3 5 Volt adapter........................................................................................162
9 Background information ...............................................................................................165
9.1 JTAG ....................................................................................................166
9.1.1 Test access port (TAP) ............................................................................166
9.1.2 Data registers........................................................................................166
9.1.3 Instruction register.................................................................................166
9.1.4 The TAP controller ..................................................................................167
9.2 The ARM core ........................................................................................169
9.2.1 Processor modes ....................................................................................169
9.2.2 Registers of the CPU core ........................................................................169
9.2.3 ARM / Thumb instruction set....................................................................170
9.3 EmbeddedICE ........................................................................................171
9.3.1 Breakpoints and watchpoints ...................................................................171
9.3.2 The ICE registers ...................................................................................172
9.4 Embedded Trace Macrocell (ETM) .............................................................173
9.4.1 Trigger condition ....................................................................................173
9.4.2 Code tracing and data tracing ..................................................................173
9.4.3 J-Trace integration example - IAR EWARM .................................................173
9.5 Embedded Trace Buffer (ETB) ..................................................................177
9.6 Flash programming ................................................................................178
9.6.1 How does flash programming via J-Link / J-Trace work? ..............................178
9.6.2 Data download to RAM ............................................................................178
9.6.3 Data download via DCC...........................................................................178
9.6.4 Available options for flash programming ....................................................178
9.7 J-Link / J-Trace firmware.........................................................................180
9.7.1 Firmware update ....................................................................................180
9.7.2 Invalidating the firmware ........................................................................180
10 Designing the target board for trace ..........................................................................183
10.1 Overview of high-speed board design........................................................184
10.1.1 Avoiding stubs .......................................................................................184
10.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths) ...............................184
10.1.3 Minimizing Crosstalk ...............................................................................184
10.1.4 Using impedance matching and termination ...............................................184
10.2 Terminating the trace signal ....................................................................185
10.2.1 Rules for series terminators .....................................................................185
10.3 Signal requirements ...............................................................................186
11 Support and FAQs .....................................................................................................187
11.1 Measuring download speed ......................................................................188
11.1.1 Test environment ...................................................................................188
11.2 Troubleshooting .....................................................................................189
11.2.1 General procedure..................................................................................189
11.2.2 Typical problem scenarios .......................................................................189
11.3 Signal analysis.......................................................................................191
11.3.1 Start sequence ......................................................................................191
11.3.2 Troubleshooting .....................................................................................191
11.4 Contacting support .................................................................................192
11.5 Frequently Asked Questions.....................................................................193
12 Glossary.....................................................................................................................195
J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG