Segger J-Link User Manual page 153

Jtag emulators for arm cores
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PIN
SIGNAL
15
RESET
17
Not used NC
5V-Sup-
19
ply
Table 8.3: J-Link / J-Trace SWD pinout
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They
should also be connected to GND in the target system.
J-Link / J-Trace (UM08001)
TYPE
Target CPU reset signal. Typically connected to the RESET
I/O
pin of the target CPU, which is typically called "nRST",
"nRESET" or "RESET".
This pin is not connected in J-Link.
This pin can be used to supply power to the target hard-
ware. Older J-Links may not be able to supply power on this
Output
pin. For more information about how to enable/disable the
power supply, please refer to Target power supply on
page 152.
Description
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
151

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