Overview Of High-Speed Board Design; Avoiding Stubs; Minimizing Signal Skew (Balancing Pcb Track Lengths); Minimizing Crosstalk - Segger J-Link User Manual

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10.1 Overview of high-speed board design

Failure to observe high-speed design rules when designing a target system contain-
ing an ARM Embedded Trace Macrocell (ETM) trace port can result in incorrect data
being captured by J-Trace.You must give serious consideration to high-speed signals
when designing the target system.
The signals coming from an ARM ETM trace port can have very fast rise and fall
times, even at relatively low frequencies.
Note: These principles apply to all of the trace port signals (TRACEPKT[0:15],
PIPESTAT[0:2], TRACESYNC), but special care must be taken with TRACECLK.

10.1.1 Avoiding stubs

Stubs are short pieces of track that tee off from the main track carrying the signal to,
for example, a test point or a connection to an intermediate device. Stubs cause
impedance discontinuities that affect signal quality and must be avoided.
Special care must therefore be taken when ETM signals are multiplexed with other
pin functions and where the PCB is designed to support both functions with differing
tracking requirements.

10.1.2 Minimizing Signal Skew (Balancing PCB Track Lengths)

You must attempt to match the lengths of the PCB tracks carrying all of TRACECLK,
PIPESTAT, TRACESYNC, and TRACEPKT from the ASIC to the mictor connector to
within approximately 0.5 inches (12.5mm) of each other. Any greater differences
directly impact the setup and hold time requirements.

10.1.3 Minimizing Crosstalk

Normal high-speed design rules must be observed. For example, do not run dynamic
signals parallel to each other for any significant distance, keep them spaced well
apart, and use a ground plane and so forth. Particular attention must be paid to the
TRACECLK signal. If in any doubt, place grounds or static signals between the
TRACECLK and any other dynamic signals.

10.1.4 Using impedance matching and termination

Termination is almost certainly necessary, but there are some circumstances where it
is not required. The decision is related to track length between the ASIC and the
JTAG+Trace connector, see Terminating the trace signal on page 185 for further ref-
erence.
J-Link / J-Trace (UM08001)
CHAPTER 10
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
Designing the target board for trace