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SP305 Spartan-3 Development Platform User Guide
Table 2-16: 10/100 SMSC Ethernet MAC Clock Signals to PHY (Continued)
18
Label
ENET_SD14
ENET_SD15
ENET_SD16 -SD31
ENET_AEN
ENET_SA1
ENET_SA2
ENET_SA3
ENET_SA4
ENET_SA5
ENET_SA6
ENET_SA7
ENET_SA8
ENET_SA9
ENET_SA10
ENET_SA11
ENET_SA12
ENET_SA13
ENET_SA14
ENET_SA15
ENET_BE0_N
ENET_BE1_N
ENET_BE2_N
ENET_BE3_N
ENET_RESET
ENET_ADS_N
ENET_LCLK_N
ENET_LCLK_N
ENET_ARDY_N
ENET_SRDY_N
ENET_RDTRTN_N
ENET_IRQ
ENET_LDEV_N
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FPGA Pin
V6
W6
Not Connected
W7
Y1
Y2
AA1
AA2
Y4
Y5
AA3
AA4
Y6
Y7
AB1
AB2
AC1
AC2
AB3
AA7
AF6
Pulled up to 3.3v
Pulled up to 3.3v
AE4
Y8
AB7
B14
AA8
AD6
AF4
AB4
AE6
SP305 Spartan-3 Development Platform User Guide
Description
Ethernet Data 14
Ethernet Data 15
Ethernet Data 16 -31
Address Enable
Ethernet Address 1
Ethernet Address 2
Ethernet Address 3
Ethernet Address 4
Ethernet Address 5
Ethernet Address 6
Ethernet Address 7
Ethernet Address 8
Ethernet Address 9
Ethernet Address 10
Ethernet Address 11
Ethernet Address 12
Ethernet Address 13
Ethernet Address 14
Ethernet Address 15
Byte Enable 0
Byte Enable 1
N/A
N/A
RESET
CLOCK
FEEDBACK
Interrupt
UG216 (v1.1) March 3, 2006
R
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