Zbt Synchronous Sram (37) - Xilinx SP305 Spartan-3 User Manual

SP305 Spartan-3 Development Platform User Guide
DDR Loop Signal
The DDR loop signal is a trace driven and then received back at the FPGA with a delay
equal to the sum of the trace delays of the clock and DQS signals. This looped trace can be
used in high-speed memory controllers to help compensate for the physical trace delays
between the FPGA and DDR chips.

ZBT Synchronous SRAM (37)

The ZBT synchronous SRAM (Cypress CY7C1354B) provides high-speed, low-latency
external memory to the FPGA. The memory is organized as 256K x 36 bits, thereby
providing for a 32-bit data bus with support for four parity bits.
Note:
Table 2-29: SRAM
30
The SRAM and FLASH memory share the same data bus.
Label
SRAM_FLASH_D0
SRAM_FLASH_D1
SRAM_FLASH_D2
SRAM_FLASH_D3
SRAM_FLASH_D4
SRAM_FLASH_D5
SRAM_FLASH_D6
SRAM_FLASH_D7
SRAM_FLASH_D8
SRAM_FLASH_D9
SRAM_FLASH_D10
SRAM_FLASH_D11
SRAM_FLASH_D12
SRAM_FLASH_D13
SRAM_FLASH_D14
SRAM_FLASH_D15
SRAM_FLASH_D16
SRAM_FLASH_D17
SRAM_FLASH_D18
SRAM_FLASH_D19
SRAM_FLASH_D20
SRAM_FLASH_D21
SRAM_FLASH_D22
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FPGA Pin
AD25
AB22
AC22
AE24
AF24
AD23
AE23
AF23
AD22
AE22
AF22
AB21
AC21
AD21
AE21
AF21
AB20
AC20
AE20
AF20
AA20
Y19
AA19
SP305 Spartan-3 Development Platform User Guide
R
Description
UG216 (v1.1) March 3, 2006