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Chapter 1: ML405 Evaluation Platform
The PC4 JTAG connection to the JTAG chain allows a host PC to download bitstreams to
the FPGA using the iMPACT software tool. PC4 also allows debug tools such as the
ChipScope™ Pro Analyzer or a software debugger to access the FPGA.
The System ACE controller can also program the FPGA through the JTAG port. Using an
inserted CompactFlash card or Microdrive storage device, configuration information can
be stored and played out to the FPGA. The System ACE controller supports up to eight
configuration images that are selected via the three configuration address DIP switches.
Under FPGA control, the System ACE chip can be instructed to reconfigure to any of the
eight configuration images.
The configuration source selector switch should be in the SYS ACE program setting if the
use of the System ACE controller is desired.
When the switch is set to the SYS ACE position, the System ACE controller programs the
FPGA from the image on the CompactFlash card at power-up. Pressing the System ACE
reset pushbutton switch also causes the System ACE controller to program the FPGA if a
CompactFlash card is present.
Platform Flash Memory
The Platform Flash memory can also be used to program the FPGA. The Platform Flash
memory can hold up to four configuration images, which are selectable by the two least
significant bits of the configuration address DIP switches.
The board is wired so the Platform Flash memory can download bitstreams in Master
Serial, Slave Serial, Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes.
Using the iMPACT tool to program the Platform Flash memory, the user has the option to
select which of the four modes to use for programming the FPGA. The configuration mode
DIP switches on the board must be set to match the programming method being used by
the Platform Flash memory.
The configuration source selector switch should be set to Plat Flash if the use of Platform
Flash memory is desired.
When set correctly, the Platform Flash memory programs the FPGA upon power-up or
whenever the Prog pushbutton switch is pressed.
Linear Flash and CPLD
Data stored in the linear flash can be read by the CPLD and used to program the FPGA.
Depending on the logic design in the CPLD, up to eight configuration images can
theoretically be supported.
The board is wired so the CPLD can download bitstreams via Master Serial, Slave Serial,
Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes. The configuration
mode DIP switches on the board must be set to match the programming method being
used by the CPLD.
The configuration source selector switch should be in the CPLD Flash setting if the use of
CPLD and Platform Flash is desired.
When set correctly, the CPLD programs the FPGA upon power-up or whenever the Prog
pushbutton switch is pressed.
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www.xilinx.com
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
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