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SP305 Spartan-3 Development Platform
User Guide
Introduction
The MicroBlaze™ development kit allows designers to investigate and experiment with
features of the Spartan™-3 family of FPGAs. This document describes features and
operation of the SP305 Development Platform.
Features
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SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
Spartan-3 FPGA (XC3S1500-FG676-10)
64MB DDR SDRAM, 32-bit interface running up to 266 MHz data rate
One differential clock input pair and differential clock output pair with SMA
connectors
One 100 MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator
socket
General purpose DIP switches, LEDs, and push buttons
Rotary Encoder with a push button shaft
Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs,
14 spare I/O's, power, JTAG chain expansion capability, and IIC bus expansion
Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, and
microphone-in (mono) jacks
Two RS-232 serial port (one stand alone and one attached to the USB Chipset)
16-character x 2-line LCD display
4Kb IIC EEPROM
VGA output with 50 MHz / 24-bit video DAC
PS/2 mouse and keyboard connectors
ZBT synchronous SRAM (9Mb) on 32-bit data bus with four parity bits
Intel StrataFlash (or compatible) linear flash memory chips (8MB)
10/100 Ethernet Mac-PHY transceiver
10/100 Ethernet PHY transceiver
USB interface chip (Cypress CY7C67300) with host and peripheral ports
CAN and SPI interface ports
IFF one wire encryption device
Xilinx XCF32P Platform Flash configuration storage device
JTAG configuration port for use with Parallel Cable III or Parallel Cable IV cable
www.xilinx.com
Introduction
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