Iff (42); Default Jumper Settings - Xilinx SP305 Spartan-3 User Manual

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SP305 Spartan-3 Development Platform User Guide

IFF (42)

The SP-305 board has an IFF Encryption device connected to an FPGA I/O pin. This IFF
device can be interfaced to an FPGA design in such a way that the functionality of the
design can be licensed or enabled by the authentication with the IFF device.
Table 2-34: SPI Pin Connections
Label Description FPGA Pin
IFF_FPGA One Wire Interface F7
36 SP305 Spartan-3 Development Platform User Guide
www.xilinx.com UG216 (v1.1) March 3, 2006