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SP305 Spartan-3 Development Platform User Guide
Table 2-23: Expansion I/O Differential Connections (J5) (Continued)
Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os; thereby
permitting the signals on this connector to carry high-speed single-ended data. All single-
ended signals on connector J6 are matched length traces. The VCCIO of these signals can
be set to 2.5V or 3.3V by setting jumper J29.
connections on this expansion I/O connector.
Table 2-24: Expansion I/O Single-Ended Connections (J6)
24
Header Pin
Label
(Diff Pair
(Diff Pair
Neg)
Neg)
J5, Pin 46
HDR2_46
J5, Pin 50
HDR2_50
J5, Pin 54
HDR2_54
J5, Pin 58
HDR2_58
J5, Pin 62
HDR2_62
Header Pin
J6, Pin 2
J6, Pin 4
J6, Pin 6
J6, Pin 8
J6, Pin 10
J6, Pin 12
J6, Pin 14
J6, Pin 16
J6, Pin 18
J6, Pin 20
J6, Pin 22
J6, Pin 24
J6, Pin 26
J6, Pin 28
J6, Pin 30
J6, Pin 32
J6, Pin 34
J6, Pin 36
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FPGA Pin
Header Pin
(Diff Pair
(Diff Pair
Neg)
Pos)
AA24
J5, Pin 48
W24
J5, Pin 52
Y23
J5, Pin 56
Y26
J5, Pin 60
AA26
J5, Pin 64
Table 2-24
summarizes the single-ended
Label
HDR1_2
HDR1_4
HDR1_6
HDR1_8
HDR1_10
HDR1_12
HDR1_14
HDR1_16
HDR1_18
HDR1_20
HDR1_22
HDR1_24
HDR1_26
HDR1_28
HDR1_30
HDR1_32
HDR1_34
HDR1_36
SP305 Spartan-3 Development Platform User Guide
FPGA Pin
Label
(Diff Pair
(Diff Pair
Pos)
Pos)
AA23
HDR2_48
W23
HDR2_52
Y22
HDR2_56
Y25
HDR2_60
AA25
HDR2_64
FPGA Pin
R21
T22
T23
V2S
U23
R19
R22
P25
U24
T26
T25
R26
P26
V24
R25
V23
R20
V22
UG216 (v1.1) March 3, 2006
R
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