Block Diagram - Xilinx SP305 Spartan-3 User Manual

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Block Diagram

Figure 2-1
Flash
32
Flash
Rotary
Encoder
GPIO
(Button/LED/
DIP Switch
100 MHz XTAL
+ User
SMA
(Differential In/
Out Clocks)
Dual PS/2
IFF
Chipscope
High Speed
Debug
5V Brick 3A
Figure 2-1: Spartan-3 SP-305 Development Platform Block Diagram
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
shows a block diagram of the board.
USB
Sync
PC
Controller
RAM
Platform
Flash
16
Spartan-3
FPGA
User IIC
I/O Expansion
IIC EEPROM
Header
5V to USB and PS/2
TPS54310
5V
3A SWIFT
TPS54310
12 V
6A SWIFT
To FPGA Core
3.3 V
TPS54310
3A SWIFT
To FPGA I/O Digital Supply
1.8 V
TPS54310
To PROM
150mA LDO
www.xilinx.com
Host
Peripheral
Peripheral
10/100/1000
Enet Phy
10/100
Enet Phy
DDR
SDRAM
32
DDR
SDRAM
Audio CODEC
RS-232 XCVR
16 x 32
Character LCD
Controller
Bus
TPS51100
3A DDR LDO
2.5 V to DDR SDRAM
Introduction
RJ-45
RJ-45
Line Out/Headphone
AC97
Mic In/Line in
VGA
Video
Serial
Can
SPI
1.25 V
To VTT
ug216_01_101105
5