Panasonic AFPX-C30R User Manual page 323

High-speed counter when using pulse I/O cassette (AFPX-PLS)
Channel No.
CH8
CH9
[Single phase]
Incremental,
CHA
Decremental
Note4)
CHB
Note4)
[2-phase]
CH8
2-phase input
One input
Direction CHA
Note4)
distinction
Related instructions:
F0(MV) :High-speed counter control
F1(DMV) :Read/write of elapsed value of high-speed counter
F166(HC1S) :Target value match on
F167(CH1R) :Target value match off
Note1) The values in parentheses are for the reset input. The reset input X102 can be set to either CH8
or CH9. The reset input X202 can be set to either CHA or CHB.
Note2) Reference: For information on minimum input pulse width,
Note3) When using the AFPX-PLS only
Note4) CHA/CHB can be used when 2 units of AFPX-PLS are installed.
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Memory area being used
Input
Control
contact
flag
Note1)
X100
R9118
(X102)
X101
R9119
(X102)
X200
R911A
(X202)
X201
R911B
(X202)
X100
R9118
X101
(X102)
X200
X201 R911A
(X202)
<10.3.3 Minimum Input Pulse Width>.
Elapsed Target
value value
area area
DT90332 DT90334
DT90333 DT90335
DT90336 DT90338
DT90337 DT90339
DT90340 DT90342
DT90341 DT90343
DT90344 DT90346
DT90345 DT90347
DT90332 DT90334
DT90333 DT90335
DT90340 DT90342
DT90341 DT90343
Performance specifications
Minimum
Maximum
input pulse
counting speed
Note2)
width
Single-phase 2
µ
6.25 s channels: 80 kHz
Single-phase 4
µ
(100 s)
channels: 50 kHz
2-phase 1
µ
16.7 s channel: 30 kHz
2-phase 2
µ
(100 s)
channels: 25 kHz