Tandy 1000 HX Technical Reference Manual page 93

8088
Interrupts result in a transfer of control to a new pro-
gram location. A 256 element table containing ad-
dress pointers to the interrupt service program loca-
tions resides in absolute locations 0 through 3FFH
(See Figure 4), which are reserved for this purpose.
Each element in the table is 4 bytes in size and cor-
responds to an interrupt "type." An interrupting de-
vice supplies an 8-bit type number, during the inter-
rupt acknowledge sequence, which is used to vector
through the appropriate element to the new interrupt
service program location.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable inter-
rupt (NMI) pin which has higher priority than the
maskable interrupt request (INTR) pin. A typical use
would be to activate a power failure routine. The
NMI is edge-triggered on a LOW to HIGH transition.
The activation of this pin causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state
of greater than two clock cycles, but is not required
to be synchronized to the clock. Any higher going
transition of NMI is latched on-chip and will be serv-
iced at the end of the current instruction or between
whole moves (2 bytes in the case of word moves) of
a block type instruction. Worst case response to
NMI would be for multiply, divide, and variable shift
instructions. There is no specification on the occur-
rence of the low-going edge; it may occur before,
during, or after the servicing of NMI. Another high-
going edge triggers another response if it occurs af-
ter the start of the NMI procedure. The signal must
be free of logical spikes in general and be free of
bounces on the low-going edge to avoid triggering
extraneous responses.
enable bit will be zero unless specifically set by an
instruction.
During the response sequence (See Figure 9), the
processor executes two successive (back to back)
interrupt acknowledge cycles. The 8088 emits the
LOCK signal (maximum mode only) from T2 of the
first bus cycle until T2 of the second. A local bus
"hold" request will not be honored until the end of
the second bus cycle. In the second bus cycle, a
byte is fetched from the external interrupt system
(e.g., 8259A PIC) which identifies the source (type)
of the interrupt. This byte is multiplied by four and
used as a pointer into the interrupt vector lookup
table. An INTR signal left HIGH will be continually
responded to within the limitations of the enable bit
and sample period. The interrupt return instruction
includes a flags pop which returns the status of the
original interrupt enable bit when it restores the
HALT
When a software HALT instruction is executed, the
processor indicates that it is entering the HALT state
in one of two ways, depending upon which mode is
strapped. In minimum mode, the processor issues
ALE, delayed by one clock cycle, to allow the sys-
tem to jatch the halt status. Halt status is available
on I O / M , DT/R, and SSO. In maximum mode, the
£rocessqr_issues appropriate HALT status on S2,
S1, and SO, and the 8288 bus controller issues one
ALE. The 8088 will not leave the HALT state when a
local bus hold is entered while in HALT. In this case,
the processor reissues the HALT indicator at the
end of the local bus hold. An interrupt request or
RESET will force the 8088 out of the HALT state.
Maskable Interrupt (INTR)
The 8088 provides a single interrupt request input
(INTR) which can be masked internally by software
with the resetting of the interrupt enable (IF) flag bit.
The interrupt request signal is level triggered. It is
internally synchronized during each clock cycle on
the high-going edge of CLK. To be responded to,
INTR must be present (HIGH) during the clock peri-
od preceding the end of the current instruction or the
end of a whole move for a block type instruction.
During interrupt response sequence, further inter-
rupts are disabled. The enable bit is reset as part of
the response to any interrupt (INTR, NMI, software
interrupt, or single step), although the FLAGS regis-
ter which is automatically pushed onto the stack re-
flects the state of the processor prior to the inter-
rupt. Until the old FLAGS register is restored, the
Read/Modify/Write (Semaphore)
Operations via LOCK
The LOCK status information is provided by the
processor when consecutive bus cycles are required
during the execution of an instruction. This allows
the processor to perform read/modify/write opera-
tions on memory (via the "exchange register with
memory" instruction), without another system bus
master receiving intervening memory cycles. This is
useful in multiprocessor system configurations to ac-
complish "test and set lock" operations. The LOCK
signal is activated (LOW) in the clock cycle following
decoding of the LOCK prefix instruction. It is deacti-
vated at the end of the last bus cycle of the instruc-
tion following theLOCK prefix. While LOCK is active,
a request on a R Q / G T pin will be recorded, and then
honored at the end of the LOCK.
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