Tandy 1000 HX Technical Reference Manual page 29

. TANDY COMPUTER PRODUCTS
CPU Control Signal Generation
The 8088 CPU uses a 4.77 (7.16) MHz clock with a special
duty cycle (4.77 -» 33% high, 67% low, - 7.16 -» 50% high,
50% low). This clock is produced by the Timing Control
Generator. The Timing Control Generator receives a 28.63636
MHz input clock and divides it by 6 to produce 4.77 MHz
CPUCLK or by 4 to produce 7.16 MHz CPUCLK, and by 24 to
produce D4CLK (1.193 MHz). In addition to being used by the
control signal logic, the clocks are buffered by U20
(74HCT244) for the bus signals OSCY (14 MHz), CLKY (CPU
clock: 4.77/7.16 MHz). (See the Bus Interface
Specification).
The RESET signals (RESET and BRESET) originate at U20
(Timing Control Generator) which synchronizes the input
RSTIN*. RSTIN* originates from C132 which is discharged to
0 volts by diode CR2 when the power is off.
The READY circuit synchronizes the system "ready" signals
with the CPU clock and generates the CPU input READY. If a
function needs one or more "wait" states added to its
access, it must set the RDYIN line low. From the main logic
board, RDYIN is set low by the sound IC for 32 extra "wait
states" and the video/system memory sets RDYIN low for
typically one or two "wait" cycles. The READY circuit of
the Timing Control Generator (U20) is operated in the
non-asynchronous mode; i.e. two sequential edges of clock (a
rising edge first) are required to set the READY signal
true. RDYIN is pulled-up by R20.
IFL Equations
U16 Buffer Control Checksum: FF6C
Inputs Outputs
PIN 1 = !mio PIN 7 = !fdcack PIN 15 = Idisnmi
PIN 2 = Imemr PIN 8 = !ior Pin 16 = !romcs
PIN 3 = al9 PIN 9 = !refresh PIN 17 = Ibufenb
PIN 4 = al8 PIN 11 = nmien PIN 18 = Ibufdir
PIN 5 = al7 PIN 13 = nmi
PIN 6 = Imemios PIN 14 = Iromdis
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