Tandy 1000 HX Technical Reference Manual page 240

• TANDY COMPUTER PRODUCTS
MEMORY TIMING PARAMETERS , READ
to
Reference time zero. STROBE lo
tOSC Period of 14.31818 MHz
tl
t2
t2A
t2B
t3
t4
t5
t5A
t6
t6A
t6B
t7
t8
t9
tio
til
tl2
tl3
tl4
tl5
tl6
tl7
ADDRESS Setup to STROBE lo
STROBE lo Setup to OSC hi
STROBE lo Length
STROBE hi Length
STROBE hi Setup to OSC hi
RAS*B lo Delay from OSC hi
RAS*B hi Delay from STROBE hi
RAS*B hi Length
CAS*B lo Delay from OSC hi
CAS*B lo Length
CAS*B lo Delay from RAS*B lo
CAS*B hi Delay from STROBE hi
MA*-Row Address
Valid Setup to RAS*B lo
MA*-Column Address
Valid Setup to CAS*B lo
MA*-Column Address Hold
DATA Valid Delay from RAS*B True
(reference)
DATA Valid Setup to STROBE hi
DATA Hold from STROBE False hi
DBDIR lo Delay from STROBE lo
DBENB lo Delay after DBDIR hi
DBENB Hold from STROBE hi
DBDIR Hold from DBENB hi
min
50
15
don't
0
0
100
0
75
20
20
35
70
0
0
0
typ
69.8
250
250
care
69.8
69.8
150
70
max
40
40
40
70
70
40
NOTE
NOTE
NOTE
NOTE
NOTE
NOTE
2
2
6
3
4
5
NOTE 1 Setup time t2 will be defined by the ASIC design.
It should be of sufficient length to allow Clear on
RAS flip-flop to go false and still meet setup time
before next clock rising edge.
NOTE 2 Address outputs are loaded with 3 row x 8 DRAMS = 24
x 8 pf = 19 2 pf. each.
NOTE 3 Additional delay through LS245 needs to be added to
match Bus Specs.
Bus requires +75 ns setup. LS245 into 45pf requires
20 ns. Therefore 75+20=95 ns.
NOTE 4 Applying the DIRection signal to the LS245 and
allowing the part to settle before applying OUTput
ENable reduces Bus and power noise. Also OUTput
ENable should be removed first.
NOTE 5 OUTput ENable should be removed first before
changing DIRection.
NOTE 6 Depends upon DRAM used.
15