Tandy 1000 HX Technical Reference Manual page 113

8253/8253-5
FUNCTIONAL DESCRIPTION
General
The 8253 is programmable interval timer/counter
specifically designed for use with the Intel™ Micro-
computer systems. Its function is that of a general
purpose, multi-timing element that can be treated as
an array of I/O ports in the system software.
The 8253 solves one of the most common problems
in any microcomputer system, the generation of ac-
curate time delays under software control. Instead of
setting up timing loops in systems software, the pro-
grammer configures the 8253 to match his require-
ments, initializes one of the counters of the 8253
with the desired quantity, then upon command the
8253 will count out the delay and interrupt the CPU
when it has completed its tasks. It is easy to see that
the software overhead is minimal and that multiple
delays can easily be maintained by assignment of
priority levels.
Other counter/timer functions that are non-delay in
nature but also common to most microcomputers
can be implemented with the 8253.
• Programmable Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller
Data Bus Buffer
The 3-state, bi-directional, 8-bit buffer is used to in-
terface the 8253 to the system data bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput CPU instructions. The Data Bus
Buffer has three basic functions.
1. Programming the MODES of the 8253.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic
The Read/Write Logic accepts inputs from the sys-
tem bus and in turn generates control signals for
overall device operation. It is enabled or disabled by
CS so that no operation can occur to change the
function unless the device has been selected by the
system logic.
RD (Read)
A "low" on this input informs the 8253 that the CPU
is inputting data in the form of a counters value.
WR (Write)
A "low" on this input informs the 8253 that the CPU
is outputting data in the form of mode information or
loading counters.
A0,A1
These inputs are normally connected to the address
bus. Their function is to select one of the three coun-
ters to be operated on and to address the control
word register for mode selection.
CS (Chip Select)
A "low" on this input enables the 8253. No reading
or writing will occur unless the device is selected.
The CS input has no effect upon the actual opera-
tion of the counters.
Figure 3. Block Diagram Showing Data Bus
Buffer and Read/Write Logic Functions
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