Tandy 1000 HX Technical Reference Manual page 115

8253/8253-5
OPERATIONAL DESCRIPTION
General
The complete functional definition of the 8253 is
programmed by the systems software. A set of con-
trol words must be sent out by the CPU to initialize
each counter of the 8253 with the desired MODE
and quantity information. Prior to initialization, the
MODE, count, and output of all counters is unde-
fined. These control words program the MODE,
Loading sequence and selection of binary or BCD
counting.
Once programmed, the 8253 is ready to perform
whatever timing tasks it is assigned to accomplish.
The actual counting operation of each counter is
completely independent and additional logic is pro-
vided on-chip so that the usual problems associated
with efficient monitoring and management of exter-
nal, asynchronous events or rates to the microcom-
puter system have been eliminated.
Programming the 8253
All of the MODES for each counter are programmed
by the systems software by simple I/O operations.
Each counter of the 8253 is individually programmed
by writing a control word into the Control Word Reg-
ister. (AO, A1 = 11)
Control Word Format
Definition Of Control
SC—SELECT COUNTER:
SC1 SCO
0
0
1
1
0
1
0
1
Select Counter 0
Select Counter 1
Select Counter 2
Illegal
RL—READ/LOAD:
RL1 RLO
0
1
0
1
0
0
1
1
Counter Latching operation (see
READ/WRITE Procedure Section).
Read/Load most significant byte only.
Read/Load least significant byte only.
Read/Load least significant byte first,
then most significant byte.
M—MODE:
M2 M1 MO
0
0
X
X
1
1
0
0
1
1
0
0
0
1
0
1
0
1
ModeO
Model
Mode 2
Mode 3
Mode 4
Mode 5
BCD:
Binary Counter 16-Bits
Binary Coded Decimal (BCD) Counter
(4 Decades)
Counter Loading
The count register is not loaded until the count value
is written (one or two bytes, depending on the mode
selected by the RL bits), followed by a rising edge
and a falling edge of the clock. Any read of the coun-
ter prior to that failing clock edge may yield invalid
data.
MODE DEFINITION
MODE 0: Interrupt on Terminal Count. The output
will be initially low after the mode set operation. After
the count is loaded into the selected count register,
the output will remain low and the counter will count.
When terminal count is reached, the output will go
high and remain high until the selected count regis-
ter is reloaded with the mode or a new count is load-
ed. The counter continues to decrement after termi-
nal count has been reached.
Rewriting a counter register during counting results
in the following:
(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.
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