Tandy 1000 HX Technical Reference Manual page 15

• TANDY COMPUTER PRODUCTS
Option Card Description
PINOUT:
IBM Bus
Signal
GND
RESETDRV
+5V
IRQ2
-5VDC
DRQ2
-12V
Reserved
+12V
GND
MEMW*
MEMR*
IOW*
IOR*
DACK3*
DRQ3
DACK1*
DRQ1
DACKO*
CLOCK
IRQ7
IRQ6
IRQ5
IRQ 4
IRQ3
DACK2*
T/C
ALE
+5V
OSC
GND
OSC
CLK
BRESET
A0-A19
Signal
GND
BRESET
+5V
IR2
NC
FDCDMARQO*
-12V
NC
+12V
GND
MEMW*
MEMR*
IOW*
IOR*
NC
NC
NC
NC
REFRESH*
CLK
RFSH*
BREQ*
NC
IR4
IR3
FDCDMACK*
TC
ALE
+ 5V
OSC
GND
0
0
0
0
PIN
B01
B02
B03
B04
B05
B06
B07
B08
B09
BIO
Bll
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
PIN
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
SIGNAL
NMI
D7
D6
D5
D4
D3
D2
Dl
DO
READY
AEN
A19
A18
A17
A16
A15
A14
A13
A12
All
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
IBM Bus
Signal
I/OCHCK*
D7
D6
D5
D4
D3
D2
Dl
DO
I/OCHRDY
AEN
A19
A18
A17
A16
A15
A14
A13
A12
All
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
Oscillator: 14.31818 Mhz High-speed clock
with a 50% duty cycle
System clock: It can be 4.77 Mhz with a 33%
duty cycle or 7.16 Mhz with a 50% duty
cycle.
Buffered Reset: This line is used to reset
or initialize system logic upon power-up or
during a lowline voltage outage. This
signal is synchronized to the falling edge
of clock and is active high.
Address bits 0 to 19: These lines are used
to address memory and I/O devices within
the system. The 20address lines allow