Tandy 1000 HX Technical Reference Manual page 226

• TANDY COMPUTER PRODUCTS
DMA CHIP SPECIFICATION
GENERAL DESCRIPTION
The DMA Chip is an Intel 8237A-5 (AMD 9517) DMA Controller
plus associated support circuity to integrate the TANDY 1000
External Memory function into a single ASIC part. The
support circuity is divided into the five functional
sections. The ADDRESS DECODE-MEMORY and ADDRESS DECODE-IO
are independent of the DMA function and interface directly
into the bus. The TIMING and DMA RDY sections are DMA
support functions. The BUFFERS support the in/out pins.
The functional configuration of the 8237 for the DMA Chip is
a fixed subset of its total capability. It is configured
via the BIOS ROM for: normal timing, fixed priority, late
write, high DREQ sense, low DACK sense.
ADDRESS DECODE - MEMORY
Provides RAM Memory access decode and address generation.
Bus addresses A19-A15 determine which segment(bank) of
memory is being accessed based on one of four possible
memory configurations, (see memory map Figure 1 ) . This is
combined with Bus strobes MEMWB or MEMRB and CLK to create
one of the three RAS strobes (RASOB, RASlB or RAS2B), MUX,
CAS, data directional controls DBDIR, DBENB and the
multiplexed RAM addresses MA0-MA8. The signals CAS and MUX
will occur for all access's except REFRESH. The address
lines MA0-MA« are Bus addresses A0-A8 and A9-A17 multiplexed
together by the signal MUX. These will occur for all
access's including REFRESH (since MUX does not occur during
REFRESH, MA0-MA8 will be only A0-A8). The selection of MA8
will be made externally since Bank 0 and Bank 1 can be
either 64K or 265K DRAM IC's.