Interface Definitions; Microprocessor Interface - Tandy 1000 HX Technical Reference Manual

SECTION 3
INTERFACE DEFINITION
3.1 MICROPROCESSOR INTERFACE
Signal
READY
WE
CE
RST-
D7
D6
D5
D4
D3
D2
Dl
DO
CLK
Pin
4
5
6
9
10
11
12
13
15
1
2
3
14
Description
OUTPUT: Open collector, READY
indicates that data has been read
when true (high). The CPU must be
placed in a wait state until
READY is true.
INPUT: Write Enable WE indicates
that data is available to the NCR
8496 when true (low).
INPUT: Chip Enable CE indicates
that data may be transferred to
the NCR 8496.
INPUT: Master Reset RST is used
for testing purposes only. This
pin is a no connect on the
SN 76489A and is internally
pulled high.
Inputs: D0-D7 is the data bust
through which data is
transferred. DO is the most
significant data bit. D7 is the
least significant data bit.
Input Clock