Tandy 1000 HX Technical Reference Manual page 214

NEC
M
PD765A/
M
PD7265
Table 4.
Phase
Seek
Command
Execution
Invalid
Command
Result
Instruction Set (Notes 1,2)(cont)
Instruction Cod*
R/W O7 Dg D5 D4 D3
w 0 0 0 0 1
W X X X X X
W NCN
w *, Invalid Codes -
R
„
S T 0
D
2
I
1
HD U
h D
0
1 1
Si US
0
Remarks
Command codes
Head is positioned over proper cylinder on diskette
Invalid Command codes (No op — FDC goes into standby state)
ST0=80H
Note:
(1) Symbols used in this table are described at the end of this section.
(2) A
o
should equal 1 for all operations.
(3) X = Don't care, usually made to equal 0.
System Configuration
Figure 2 shows an example of a system using a
MPD765A/
M
PD7265.
Figure 2. System Configuration
Processor Interface
During command or result phases the main status reg-
ister (described earlier) must be read by the processor
before each byte of information is written into or read
from the data register. After each byte of data read or
written to the data register, CPU should wait for 12^s be-
fore reading main status register, bits D6 and D7 in the
main status register must be in a 0 and 1 state, respec-
tively, before each byte of the command word may be
written into the /iPD765A/jiPD7265. Many of the com-
mands require multiple bytes and, as a result, the main
status register must be read prior to each byte transfer
to the MPD765A/jiPD7265. On the other hand, during the
result phase, D6 and D7 in the main status register must
both be 1' s (D6 = 1 and D7 = 1) before reading each byte
from the data register. Note that this reading of the main
status register before each byte transfer to the
nPD765A/^PD7265 is required only in the command and
result phases, and not during the execution phase.
During the execution phase, the main status register
need not be read. If the MPD765A//,<PD7265 is in the non-
DMA mode, then the receipt of each data byte (if
MPD765A/^PD7265 is reading data from FDD) is indi-
cated by an interrupt signal on pin 18 (INT = 1). The gen-
eration of a read signal (RD = 0) or write signal (WR = 0)
will clear the interrupt as well as output the data onto
the data bus. If the processor cannot handle interrupts
fast enough (every 13^s for the MFM mode and 27fiS for
the FM mode), then it may poll the main status register
and bit D7 (RQM) functions as the interrupt signal. If a
write command is in process then the WR signal ne-
gates the reset to the interrupt signal.
Note that in the non-DMA mode it is necessary to exam-
ine the main status register to determine the cause of
the interrupt, since it could be a data interrupt or a com-
mand termination interrupt, either normal or abnormal.
If the nPD765A/nPD7265 is in the DMA mode, no inter-
rupts are generated during the execution phase. The
fiPD765A/jiPD7265 generates DRQs (DMA requests)
when each byte of data is available. The DMA controller
responds to this request with both a DACK = 0 (DMA ac-
knowledge) and an RD = 0 (read signal). When the DMA
acknowledge signal goes low (DACK = 0), then the DMA
request is cleared (DRQ = 0). If a write command has
been issued then a WR signal will appear instead of RD.
After the execution phase has been completed (terminal
count has occurred) or the EOT sector read/written,
then an interrupt will occur (INT = 1). This signifies the
beginning of the result phase. When the first byte of
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