Tandy 1000 HX Technical Reference Manual page 232

• TANDY COMPUTER PRODUCTS
PIN DEFINITIONS
NOTE: All negative true signals use the suffix "B"
INPUTS: (11 pins)
MCFO
MCF1
RFSH
Memory configuration OPTION Select.
(See Figure 1 for details.)
8237 CHANNEL 0 REQUEST (DREQ2)
Input from timer. Set up as 16 microsec
interval timer for REFRESH.
DRQ1 8237 CHANNEL 1 REQUEST (DREQl)
FDCDMARQ 82 37 CHANNEL 2 REQUEST (DREQ2) dedicated
to FDC.
DRQ3 8237 CHANNEL 3 REQUEST (DREQ3)
READY System READY signal for DMA.
RESET System hardware master RESET.
OSC Memory timing clock. Currently CLK14M.
AEN CPU Bus Grant (8237 HLDA)
TEST Input for TEST mode used by IC mfg.
BI-DIRECTIONAL: (32 pins)
BUSA19-BUSA16 System Segment Address (CPU BUS MASTER-
INPUT, DMA BUS MASTER- OUTPUT)
BUSA15-BUSA0 System Address (CPU BUS MASTER-
INPUT, DMA BUS MASTER- OUTPUT)
D00-D07 System Data Bus (WRITE-OUTPUT,
READ- INPUT)
MRB System Memory Read strobe (CPU BUS
MASTER- INPUT, DMA BUS MASTER- OUTPUT)
MWB System Memory Write strobe (CPU BUS
MASTER- INPUT, DMA BUS MASTER- OUTPUT)
IRB System Memory Read strobe (CPU BUS
MASTER- INPUT, DMA BUS MASTER- OUTPUT)
IWB System Memory Write strobe (CPU BUS
MASTER- INPUT, DMA BUS MASTER- OUTPUT)