Tandy 1000 HX Technical Reference Manual page 43

• TANDY COMPUTER PRODUCTS
Floppy Disk Controller Interface
The FDC interface consists of the NEC UPD765A controller
and Custom FDC Support Chip (FDSL). The clocks are
generated by the FDSL. The FDSL receives a raw clock of 16
MHz. The clock outputs to the FDC Controller consist of
Write Clock (WCK) at 250 nsec every 2 usec, and FDC Clock
(FDCCLK) at 4.00 MHz which is applied to the FDC Controller
for its internal processor clock (CLK pin 19).
The FDSL receives the step signal (FRES/S) from the FDC
Controller and generates the step pulses (STEP*) to the FDD
to move the heads. The FDSL receives the Track 0 signal from
the FDD (TRKO*) and relays it to the FDC Controller with the
F/TRKO signal.
The FDSL also handles DMA Request and Interrupt
Enable (DMA/INTE) as well as Interrupt Request (INT+)
generated by the FDC Controller. The FDSL receives DMA
Request (DRQ) from the FDC Controller and generates a 1 usec
delayed DMA Request (FDCDMRQ*) to the Expansion Bus.
The FDSL converts Serial Read Data (RDDATA*) from the FDD
into Serial Read Data (RDD) and Read Data Window (RDW) and
sends it on to the FDC Controller.
The FDC Controller supplies Write Enable (WRE), Serial Data
(WRD) and Write Pre-compensation (PSO, P S D to the FDSL to
produce Serial Output Data (WRDATA*) to the FDD. The FDC
Controller also generates the (RW*/SEEK) signal to the FDSL
to put the FDC in Seek Mode. (High signal to indicate Seek
Mode).
Pin Definitions for the FDSL are found in Table 1. Pin
definitions for the UPD765A may be found in the Device
Specifications Section.
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