Tandy 1000 HX Technical Reference Manual page 246

• TANDY COMPUTER PRODUCTS
DMA BUS MASTER TIMING, READ / WRITE
21
tl
t2
t3
t4
t5
t6
t7
t8
t9
tio
til
tl2
DRQ* True Setup to CLK lo
DRQ* False Setup to CLK lo
BREQB True Delay from CLK hi
BREQB False Delay from CLK hi
AEN True Delay after BREQB True
AEN True Setup to CLK Hi
AEN False delay from CLK hi
DACK*B True Delay from CLK lo
DACK*B True Hold from AEN True
DACK*B False delay from CLK lo
ADDRESS Valid Setup to CLK Hi
ADDRESS False delay from CLK hi
tl2 MEMRB or IORB True Delay from
CLK hi
tl3 MEMRB or IORB False Delay after
CLK hi
tl4 MEMWB or IOWB True Delay from
CLK hi
tl5 MEMWB or IOWB False Delay after
CLK hi
tl6
tl7
tl8
tl9
EOP True Delay after CLK hi
EOP False Delay after CLK hi
BRDY False Setup to CLK hi
BRDY False Hold after CLK hi
| min typ
30
30
N x tCYC
0
50
0
30
30
max
120
120
+30
40
40
170
170
40
40
4 Q
40
40
40
8237A-5 tDQl
8237A-5 tDQl
N =
8237A-5 tAK
8237A-5 NOTE 6
8237A-5 tAK
System Spec