Tandy 1000 HX Technical Reference Manual page 264

FIGURE 6. OSCILLATOR/CLOCK RELATIONSHIPS, 28 MHZ
t3 CPUCLK low to RQ/GTB
t4 RQ/GTB (True) setup
t5 RQ/GTB (FaJse) hold
t6 CPUCLK hi to HLDA De
t7 HOLDB (False) Setup
Inactive (REQ/REL pulse) 1
to CPUCLK hi (ACK pulse) 1
from CPUCLK low (ACK pulse)1
lay 1
to CPUCLK low 1
20
20
50 ns
ns
50 ns
30 ns
ns
tCHGX 8088
tCLGL 8088
tCLGH 8088
CLOCK PARAMETER
tl
t2
t3
t4
t5
t6
t7
t8
OSC28M Period
CLK14M Period
CLK14M high (Includes tRISE)
CLK14M low (Includes tFALL)
OSC28M to CLK*M Output Delay skew
CLK*M to CLK*M Output Delay skew
CLK3580K Period
CLK3580K high (Includes tRISE)
min
-10%
-10X
typ
34.9
tl x 2
t2/2
(t2-t3)
15
15
tl x 8
t7/2
max
NOTE 1
+ 10X
+ 10%