Tandy 1000 HX Technical Reference Manual page 221

M
PD765A/
M
PD7265
NEC
ter 3 contains the drive status information stored inter-
nally in FDC registers.
Invalid
If an Invalid command is sent to the FDC (a command
not defined above), then the FDC will terminate the com-
mand after bits 7 and 6 of status register 0 are set to 1
and 0, respectively. No interrupt is generated by the
jiPD765A/piPD7265 during this condition. Bits 6 and 7
(DIO and RQM) in the main status register are both 1
(high), indicating to the processor that the /iPD765A/
/iPD7265 is in the result phase and the contents of sta-
tus register 0 (STO) must be read. When the processor
Figure 5. Data Format (Sheet 1 of 2)
reads status register 0 it will find an 80H, indicating an
Invalid command was received.
A Sense Interrupt Status command must be sent after a
seek or recalibrate interrupt, otherwise the FDC will
consider the next command to be an Invalid command.
In some applications the user may wish to use this com-
mand as a No-Op command to place the FDC in a
standby or no operation state.
Data Format
Figure 5 shows the data transfer format for the /iPD765A
and MPD7265 in various modes.
N o t * : It is suggested that the user refer to the following application notes:
(1) #8 — for an example of an actual interface, as well as a "theoretical" data
(2) #10 — for a well documented example of a working phase-locked loop.
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