Tandy 1000 HX Technical Reference Manual page 308

. TANDY COMPUTER PRODUCTS
39
MAO-MAI3,
14,15
AENB
LD0-LD13,
14,15
LOAD
BREAK
READB
VDRA
(reserved)
DW
OP
IP
I/O
IP
IP
OP
n/c
IP
14, 15, or 16- bit Video Memory
Address bus. These tri-state outputs
provide the binary address to the
external video RAM. If row/column
addressing is selected (SY version
only) this bus will provide
row/column addressing to the external
RAM instead of binary addressing.
The AENB input signal can be used to
place the MA bus in the high
impedance state.
Address Enable input - when asserted
low (AENB = "0") the MA outputs are
enabled. AENB = " 1 " forces the MA
outputs into a high impedance state.
14, 15, or 16-bit Advanced Memory
Address bus - separate video memory
address information on this bus
precedes the information on the MA
bus by one character clock. This bus
is provided to interface with a
separate strip of logic for split
display capability.
When asserted (high) a new value is
loaded into the RA counter. Tie to
VSS when not used.
To be used for splitted screen
format. Tie to VSS when not used.
This signal goes LOW during a
legitimate read operation.
Reserved for future expansion. To
be left unconnected.
Double Width input - this input puts
the VE68C45 in a double-width display
mode. Tie to VSS when not used.