Tandy 1000 HX Technical Reference Manual page 116

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MODE 1: Programmable One-Shot. The output will
go low on the count following the rising edge of the
gate input.
The output will go high on the terminal count. If a
new count value is loaded while the output is low it
will not affect the duration of the one-shot pulse until
the succeeding trigger. The current count can be
read at any time without affecting the one-shot
pulse.
The one-shot is retriggerable, hence the output will
remain low for the full count after any rising edge of
the gate input.
MODE 2: Rate Generator. Divide by N counter. The
output will be low for one period of the input clock.
The period from one output pulse to the next equals
the number of input counts in the count register. If
the count register is reloaded between output pulses
the present period will not be affected, but the sub-
sequent period will reflect the new value.
The gate input, when low, will force the output high.
When the gate input goes high, the counter will start
from the initial count. Thus, the gate input can be
used to synchronize the counter.
When this mode is set, the output will remain high
until after the count register is loaded. The output
then can also be synchronized by software.
MODE 3: Square Wave Rate Generator. Similar to
MODE 2 except that the output will remain high until
one half the count has been completed (or even
numbers) and go low for the other half of the count.
This is accomplished by decrementing the counter
by two on the falling edge of each clock pulse. When
the counter reaches terminal count, the state of the
output is changed and the counter is reloaded with
the full count and the whole process is repeated.
If the count is odd and the output is high, the first
clock pulse (after the count is loaded) decrements
the count by 1. Subsequent clock pulses decrement
the clock by 2. After timeout, the output goes low
and the full count is reloaded. The first clock pulse
(following the reload) decrements the counter by 3.
Subsequent clock pulses decrement the count by 2
until timeout. Then the whole process is repeated. In
this way, if the count is odd, the output will be high
for (N + 1)/2 counts and low for (N - 1)/2 counts.
In Modes 2 and 3, if a CLK source other than the
system clock is used, GATE should be pulsed imme-
diately following WR of a new count value.
MODE 4: Software Triggered Strobe. After the
mode is set, the output will be high. When the count
is loaded, the counter will begin counting. On termi-
nal count, the output will go low for one input clock
period, then will go high again.
If the count register is reloaded during counting, the
new count will be loaded on the next CLK pulse. The
count will be inhibited while the GATE input is low.
MODE 5: Hardware Triggered Strobe. The counter
will start counting after the rising edge of the trigger
input and will go low for one clock period when the
terminal count is reached. The counter is retriggera-
ble. The output will not go low until the full count
after the rising edge of any trigger.
Signa
Status
Modes
0
1
2
3
4
5
Low
Or Going
Low
Disables
counting
1) Disables
counting
2) Sets output
immediately
high
1) Disables
counting
2) Sets output
immediately
high
Disables
counting
—
Rising
—
1) Initiates
counting
2) Resets output
after next
clock
1) Reloads
counter
2) Initiates
counting
1) Reloads
counter
2) Initiates
counting
—
nitiates
counting
High
Enables
counting
Enables
counting
Enables
counting
Enables
counting
—
Figure 6. Gate Pin Operations Summary
2-18