Tandy 1000 HX Technical Reference Manual page 296

• TANDY COMPUTER PRODUCTS
LOGIC BLOCK DIAGRAM
TEST MODES AND THEIR OPERATIONS
There are four Test Modes that the chip can be placed into to
make the part easily and efficiently testable. All these Test
Modes use conditions that can never occur in a System environ-
ment, therefore avoiding accidental entry in Test Mode. All the
test modes are entered when both MEMRB and MEMWB are active. The
selection of the different tests is done by an additional decode
on some bits of the BA lines according to the following chart:
TEST
MODE
1
2
3
4
ENABLED WHEN
BMEMRB
0
0
0
0
BMEMWB
0
0
0
0
BA15
1
0
0
0
BA14
X
1
X
X
BA13
X
X
1
X
BA12
X
X
X
0/1
OPERATION PERFORMED
Pinout the 6845 Megacell on
external pins and/or Start
Self Test Rom. While the
testing of the Megacell is
in progress, the Rom is
performing a signature
analysis. At the end of
4 500 clocks, a PASS/FAIL
bit is set, if the Self
Test was successful.
Enable a Software Reset on
the 6845.
Clear the Clock generators
& blink counter to start
from a known condition.
A logical 1 writes a bit that
forces Display Enable con-
stantly. A 0 removes forced
Display Enable. Cleared by
SYSRSTB.
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