Tandy 1000 HX Technical Reference Manual page 257

. TANDY COMPUTER PRODUCTS •
1.2 DESCRIPTION OF PINS'
Pin # Pin Name Type
Descr i P t i on
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VIDUAITB
FAST
D4CLK
FDCDRQ
DFDCDRQ
A02
ALE
DENB
IOUB
IORB
CLK8M
CLK14M
CLK3580K
0SC16M
VDD
CPUCLK
CLK477DK
S2B
SIB
SOB
RSTINB
RESET
READ
INTAB
RQ/GTB
vss
0SC28M
HLDA
READY
INTCSB
MEMUB
MEMRB
IOB/M
RDYIN
FDCCSB
DORCLK
FDCCHPB
FDCUCK
CLK4M
HOLDB
INPUT
INPUT
OUTPUT
INPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
POUER
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT/OUTPUT
GROUND
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
Wait signal from video system (0 = Uait>
Clock speed select
C L K 4 7 7 M / 4 , Squarewave
FDC DMA Request
Beginning of FDCDRQ delayed 1.0 microsec
System Address
Address Latch Enable
Data Enable
I/O Wr i te
I/O Read
0 S C 1 6 M / 2 , Squarewave
0SC28M/2* Squarewave
0 S C 2 B M / B , Squarewave
Input Frequency = 16.00000 MHz
FAST=1> CPUCLK=7.16MHz (0SC2BM/4, 50-50 cycle)
F A S T = 0 , CPUCLK=4.77MHz (0SC28M/6, 33-67 cycle)
C L K 1 4 M / 3 , 3 3 % duty cycle
8088 Status Signal
8088 Status Signal
8088 Status Signal
Asynchronous system input
8088 CPU Reset input
Directional Control -for CPU Data buffer
Interrupt Acknowledge
Request/Acknow I edge/Re I ease
Input frequency = 28.63636 MHz
Bus Acknoui I edge
8088 CPU READY input
8257 Interrupt Controller Chip Select
Memory Ur i te
Memory Read
1 = Memory access? 0 = I/O access
Asynchronous system input <0 = Wait condition)
Previously decoded FDC Function I/O chip select
Configuration register Chip Select
FDC Chip Select
Pulse> Period = 2 micras.ec> 2 5 0 ( n a m ) pulse
0SC16M/4> Squarewave
Bus Request