Tandy 1000 HX Technical Reference Manual page 190

Instruction Set (cont)
Mnemonic
Accumulator (cont)
ORLA,@Rr
RLA
RLCA
RRA
RRCA
SWAP A
XRLA,#data
XRLA, Rr
XRLA,@Rr
Branch
DJNZ Rr, addr
JBb addr
Function
(A) — (A) OR ((Rr))
r = 0-1
(AN +1) — (AN)
(A
0
) — (A
7
) N = 0-6
(AN+1) —(AN); N = 0-6
(A
0
) — (C)
(C) — (A
7
)
(AN) — ( A N + 1 ) ; N = 0-6
(A
7
) * ~ (A
0
)
(AN) — (AN +1); N = 0-6
(C) — (A
0
)
( A 4 - A 7 ) — (A
0
-A
3
)
(A) — (A) XOR data
(A) —(A)XOR(Rr)
r = 0-7
(A) —(A)XOR((Rr))
r = 0-1
(Rr) — (Rr) - 1; r = 0-7
lf(Rr)#O;
(PC
0
-PC
7
)— addr
(PC0-PC7) — addr if b = 1
(PC) = (PC) + 2 if b = 0
Description
Takes the logical sum (logical OR) of the contents of the internal
data memory location specified by bits 0-5 in register Rr, and the
contents of the accumulator, and stores the result in the
accumulator.
Rotates the contents of the accumulator one bit to the left. The
MSB is rotated into the LSB.
Rotates the contents of the accumulator one bit to the left through
carry.
Rotates the contents of the accumulator one bit to the right. The
LSB is rotated into the MSB.
Rotates the contents of the accumulator one bit to the right through
carry.
Exchanges the contents of the lower 4 bits of the accumulator with
the upper 4 bits of the accumulator.
Takes the exclusive OR of immediate data d
o
- d
7
and the contents
of the accumulator, and stores the result in the accumulator.
Takes the exclusive OR of the contents of register Rr and the
accumulator, and stores the result in the accumulator.
Takes the exclusive OR of the contents of the location in data
memory specified by bits 0-5 in register Rr, and the accumulator,
and stores the result in the accumulator.
Decrements the contents of register Rr by 1, and if the result is not
equal to 0, jumps to the address indicated by ao~a7.
Jumps to the address specified by ao~a7 if the bit in the
accumulator specified by bQ-b2 is set.
Hex
Code
4n(4)
E7
F7
77
67
47
D3
Dn(4)
Dn(4)
En
x2(6)
D7
0
1
1
0
0
0
1
d
7
1
1
1
b
2
1
1
1
1
1
1
1
d
6
1
1
1
*
Operation Code
Ds
0
1
1
1
1
0
0
d
5
0
0
1
bo
as
D
4
0
0
1
1
0
0
1
d
4
1
1
0
a
4
1
a
4
D
3
0
0
0
0
0
0
0
d
3
1
0
1
0
D
2
0
1
1
1
1
1
0
d
2
r
0
r
a
2
0
a
2
Di
0
1
1
1
1
1
1
r
0
r
a
i
1
Do
r
1
1
1
1
1
1
do
r
r
r
ao
0
ao
Cycles
1
1
1
1
1
1
2
1
1
2
2
Bytes
1
1
1
1
1
1
2
1
1
2
2