Tandy 1000 HX Technical Reference Manual page 114

8253/8253-5
cs
0
0
0
0
0
0
0
0
1
0
RD
1
1
1
1
0
0
0
0
X
1
WR
0
0
0
0
1
1
1
1
X
1
A i
0
0
1
1
0
0
1
1
X
X
Ao
0
1
0
1
0
1
0
1
X
X
Load Counter No. 0
Load Counter No. 1
Load Counter No. 2
Write Mode Word
Read Counter No. 0
Read Counter No. 1
Read Counter No. 2
No-Operation 3-State
Disable 3-State
No-Operation 3-State
Control Word Register
The Control Word Register is selected when AO, A1
are 11. It then accepts information from the data bus
buffer and stores it in a register. The information
stored in this register controls the operation MODE
of each counter, selection of binary or BCD counting
and the loading of each count register.
The Control Word Register can only be written into;
no read operation of its contents is available.
Counter #0, Counter # 1 , Counter #2
These three functional blocks are identical in opera-
tion so only a single counter will be described. Each
Counter consists of a single, 16-bit, pre-settable,
DOWN counter. The counter can operate in either
binary or BCD and its input, gate and output are con-
figured by the selection of MODES stored in the
Control Word Register.
The counters are fully independent and each can
have separate MODE configuration and counting op-
eration, binary or BCD. Also, there are special fea-
tures in the control word that handle the loading of
the count value so that software overhead can be
minimized for these functions.
The reading of the contents of each counter is avail-
able to the programmer with simple READ opera-
tions for event counting applications and special
commands and logic are included in the 8253 so
that the contents of each counter can be read "on
the fly" without having to inhibit the clock input.
8253 SYSTEM INTERFACE
The 8253 is a component of the IntelTM Microcom-
puter systems and interfaces in the same manner as
all other peripherals of the family. It is treated by the
systems software as an array of peripheral I/O
ports; three are counters and the fourth is a control
register for MODE programming.
Basically, the select inputs AO, A1 connect to the
AO, A1 address bus signals of the CPU. The C5 can
be derived directly from the address bus using a lin-
ear select method. Or it can be connected to the
output of a decoder, such as an Intel 8205 for larger
systems.
Figure 4. Block Diagram Showing Control Word
Register and Counter Functions
Figure 5.8253 System Interface
2-16