Tandy 1000 HX Technical Reference Manual page 131

8259A
Content of Second Interrupt Vector Byte
I R
7
6
5
4
3
2
1
0
I R
7
6
5
4
3
2
1
0
D7
A7
A7
A7
A7
A7
A7
A7
A7
D7
A7
A7
A7
A7
A7
A7
A7
A7
D6
A6
A6
A6
A6
A6
A6
A6
A6
D6
A6
A6
A6
A6
A6
A6
A6
A6
D5
A5
A5
A5
A5
A5
A5
A5
A5
D5
1
1
1
1
0
0
0
0
Interval =
D4
1
1
1
1
0
0
0
0
D3
1
1
0
0
1
1
0
0
Interval =
D4
1
1
0
0
1
1
0
0
D3
1
0
1
0
1
0
1
0
4
D2
1
0
1
0
1
0
1
0
8
D2
0
0
0
0
0
0
0
0
D1
0
0
0
0
0
0
0
0
D1
0
0
0
0
0
0
0
0
DO
0
0
0
0
0
0
0
0
DO
0
0
0
0
0
0
0
0
During the third I NT A pulse the higher address of the
appropriate service routine, which was programmed
as byte 2 of the initialization sequence (AS-A15), is
enabled onto the bus.
Content of Third Interrupt Vector Byte
D7 D6 D5 D4 D3 D2 D1 DO
| A15 | A14 | A13 | A12 | A11 | A10 | A9 | A8 |
composed as follows (note the state of the ADI
mode control is ignored and A5-A-11 are unused in
8086 mode):
Content of Interrupt Vector Byte
for 8086 System Mode
IR7
IR6
IR5
IR4
IR3
IR2
I R 1
IRO
D7
T7
T7
T7
T7
T7
T7
T7
T7
D6
T6
T6
T6
T6
T6
T6
T6
T6
D5
T5
T5
T5
T5
T5
T5
T5
T5
D4
T4
T4
T4
T4
T4
T4
T4
T4
D3
T3
T3
T3
T3
T3
T3
T3
T3
D2
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
DO
1
0
1
0
1
0
1
0
PROGRAMMING THE 8259A
The 8259A accepts two types of command words
generated by the CPU:
1. Initialization Command Words (ICWs): Before
normal operation can begin, each 8259A in the
system must be brought to a startincyaoint—by a
sequence of 2 to 4 bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are
the command words which command the 8259A
to operate in various interrupt modes. These
modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime
after initialization.
8086,8088
8086 mode is similar to MCS-80 mode except that
only two Interrupt Acknowledge cycles are issued by
the processor and no CALL opcode is sent to the
processor. The first interrupt acknowledge cycle is
similar to that of MCS-80, 85 systems in that the
8259A uses it to internally freeze the state of the
interrupts for priority resolution and as a master it
issues the interrupt code on the cascade lines at the
end of the INTA pulse. On this first cycle it does not
issue any data to the processor and leaves its data
bus buffers disabled. On the second interrupt ac-
knowledge cycle in 8086 mode the master (or slave
if so programmed) will send a byte of data to the
processor with the acknowledged interrupt code
INITIALIZATION COMMAND WORDS
(ICWS)
General
Whenever a command is issued with A0 = 0 and D4
= 1, this is interpreted as Initialization Command
Word 1 (ICW1). ICW1 starts the intiitalization se-
quence during which the following automatically oc-
cur.
a. The edge sense circuit is reset, which means that
following initialization, an interrupt request (IR) in-
put must make a low-to-high transistion to gener-
ate an interrupt.
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