Tandy 1000 HX Technical Reference Manual page 124

8259A
Table 1 Pin Description
Symbol
v
C
c
QND
WR
D7-D0
CAS
0
-CAS
2
SP/O^J
INT
IR0-IR7
\WTA
Ao
Pin No.
28
14
1
2
3
4-11
12,13,15
16
17
18-25
26
27
Type
I
I
i
I
I
I/O
I/O
I/O
0
I
I
I
Name and Function
SUPPLY: +5V Supply.
GROUND
CHIP SELECT: A low on this pin enables RD and WE communication
between the CPU and the 8259A. INTA functions are independent of
CS.
WRITE: A low on this pin when CS is low enables the 8259A to accept
command words from the CPU.
READ: A low on this pin when CS is low enables the 8259A to release
status onto the data bus for the CPU.
BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector
information is transferred via this bus.
CASCADE LINES: The CAS lines form a private 8259A bus to control
a multiple 8259A structure. These pins are outputs for a master 8259A
and inputs for a slave 8259A.
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin.
When in the Buffered Mode it can be used as an output to control
buffer transceivers (EN). When not in the buffered mode it is used as
an input to designate a master (SP =• 1) or slave (SP = 0).
INTERRUPT: This pin goes high whenever a valid interrupt request is
asserted. It is used to interrupt the CPU, thus it is connected to the
CPU's interrupt pin.
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request
is executed by raising an IR input (low to high), and holding it high until
it is acknowledged (Edge Triggered Mode), or just by a high level on an
IR input (Level Triggered Mode).
INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A
interrupt-vector data onto the data bus by a sequence of interrupt
acknowledge pulses issued by the CPU.
AO ADDRESS LINE: This pin acts in conjunction with the €5, WR, and
RD pins. It is used by the 8259A to decipher various Command Words
the CPU writes and status the CPU wishes to read. It is typically
connected to the CPU AO address line (A1 for 8086,8088).
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